Bonded Semiconductor Chip Alignment Marks for Fast Connection Inspection
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Solution Overview
Problem
Existing methods for inspecting electrical connections between bonded semiconductor chips are time-consuming, as they require operating internal circuits and performing logical computations.
Innovation Solution
A semiconductor device design featuring alignment marks and measurement terminals on both base-side and bonding-side chips, allowing for direct electrical connection verification by overlapping alignment marks and using measurement terminals to apply and measure voltages, reducing the need for complex internal circuit operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If inspection is performed by operating internal circuits, then measurement reliability is improved, but inspection time increases
Solution Approach 1:
The patent extracts the measurement function from the internal circuits of the bonded chips and relocates it to external measurement terminals on the base-side chip. This allows inspection without operating internal circuits, significantly reducing inspection time while maintaining measurement reliability through direct electrical connection verification between alignment marks.
Solution Approach 2:
The patent introduces measurement terminals as intermediary elements that facilitate electrical connection inspection between bonded chips. These terminals provide external access points that connect to alignment marks through wirings, enabling inspection without directly interacting with internal circuits of the bonding-side chip.
2Productivity
If alignment marks are electrically connected to measurement terminals, then inspection speed is improved, but device complexity increases
Solution Approach 1:
The patent segments the measurement function into separate components: alignment marks on both chips, measurement terminals on the base-side chip, and wirings that electrically connect them. This segmentation allows independent optimization of each component and simplifies the overall inspection system by separating measurement infrastructure from the bonded chip functionality.
Solution Approach 2:
The measurement terminals serve multiple functions: they act as electrical connection points for inspection, provide access to alignment mark signals, and enable both pre-bonding and post-bonding verification. This multi-functionality reduces the need for separate inspection infrastructure, offsetting the added complexity with operational versatility.
Data Source
AI summary
A semiconductor device includes: a first semiconductor chip on which a first alignment mark, a second alignment mark, first and second terminals for measuring conduction, a wiring that electrically connects the first alignment mark and the first terminal, and a wiring that electrically connects the second alignment mark and the second terminal are provided; and a second semiconductor chip on which a third alignment mark, a fourth alignment mark, and a wiring that electrically connects the third alignment mark and the fourth alignment mark are provided and which is bonded to the first semiconductor chip in such a way that the first alignment mark and the third alignment mark overlap each other, and the second alignment mark and the fourth alignment mark overlap each other.