Semiconductor Chip Alignment Mark Asymmetry for Mounting Accuracy
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Solution Overview
Problem
In semiconductor device assembly, the use of a common alignment mark on a wiring substrate for both the first and second semiconductor chips leads to position deviation and inaccurate mounting, especially with narrow pitch through electrodes, causing unstable electrical coupling and potential false recognition during alignment.
Innovation Solution
A recognition mark is formed on the back surface of the first semiconductor chip, distinct from the array shape of the electrode pads, allowing for accurate alignment and mounting of the second semiconductor chip by imaging and recognizing the unique shape of the recognition range, ensuring precise alignment and reducing false recognition.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a common alignment mark on the wiring substrate is used for both the first and second semiconductor chips, then the device complexity is reduced, but the manufacturing precision and reliability deteriorate due to position deviation and false recognition
Solution Approach 1:
The alignment mark system is segmented into multiple distinct marks: a first alignment mark for the first semiconductor chip and a second alignment mark for the second semiconductor chip. This segmentation allows each chip to have its own dedicated alignment reference, eliminating the position deviation issues that arise from using a single common alignment mark for multiple chips with different mounting requirements.
Solution Approach 2:
A recognition mark is introduced as an intermediary element that assists in distinguishing between different alignment marks during the mounting process. The recognition mark has a shape different from the electrode pad array, enabling the mounting apparatus to correctly identify and use the appropriate alignment mark for each chip, thereby preventing false recognition while maintaining systematic organization.
2Ease of operation
If a common alignment mark is used for multiple chips, then the ease of operation is improved, but the reliability of electrical coupling deteriorates due to position deviation
Solution Approach 1:
The alignment process is segmented into distinct steps for each chip, with each step using its own dedicated alignment mark. The first alignment mark is used for mounting the first semiconductor chip, and the second alignment mark is used for mounting the second semiconductor chip. This segmentation ensures that each chip is aligned with high precision relative to its specific mounting position, maintaining reliable electrical coupling while keeping the overall operation systematic.
3Difficulty of detecting and measuring
If the recognition mark shape is similar to the electrode pad array shape, then the ease of detection is improved, but the measurement precision deteriorates due to false recognition
Solution Approach 1:
The recognition mark is designed with an asymmetric shape that is distinctly different from the regular array pattern of electrode pads. This asymmetry creates a unique visual signature that can be easily distinguished by the mounting apparatus's recognition system, preventing false recognition of electrode pad arrays as alignment marks while maintaining clear detectability through its distinctive geometric features.
Data Source
AI summary
To improve the assemblability of a semiconductor device.When a memory chip is mounted over a logic chip, a recognition range including a recognition mark formed at a back surface of the logic chip is imaged and a shape of the recognition range is recognized, alignment of a plurality of bumps of the logic chip and a plurality of projection electrodes of the above-described memory chip is performed based on a result of the recognition, and the above-described memory chip is mounted over the logic chip. At this time, the shape of the recognition range is different from any portion of an array shape of the bumps, as a result, the recognition mark in the shape of the recognition range can be reliably recognized, and alignment of the bumps of the logic chip and the projection electrodes of the above-described memory chip is performed with high accuracy.