Chip Package Anchor Structure for Multi-Chip Warpage Control
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Solution Overview
Problem
Forming a reliable chip package structure with multiple chips is challenging due to issues with warpage and thermal stress, which affect the coplanarity of conductive bumps and the structural stability of the package.
Innovation Solution
The use of anchor structures and an antiwarpage structure, which includes a lower portion surrounding the chip and an upper portion with a flat structure, bonded to the adhesive layers, helps reduce warpage and thermal stress by improving bonding accuracy and limiting the antiwarpage structure's movement, thereby enhancing the structural stability and reliability of the chip package.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If multiple chips are integrated into a single package structure, then the functionality and complexity of the electronic device are improved, but the structural stability and reliability deteriorate due to warpage and thermal stress
Solution Approach 1:
The patent divides the package structure into distinct functional layers including a substrate, multiple chip structures mounted on the substrate, and an encapsulant material that surrounds the chips. This segmentation allows each layer to be optimized independently for its specific function while maintaining overall structural integrity and reducing warpage issues through distributed stress management.
Solution Approach 2:
The patent modifies physical parameters of the package structure including the coefficient of thermal expansion (CTE) matching between substrate and chips, the modulus of elasticity of the encapsulant material, and the thickness ratios of different layers. These parameter changes reduce thermal stress and warpage while maintaining structural stability during temperature cycling and operation.
2Adaptability or versatility
If multiple chips with multiple functions are integrated, then the device capability is improved, but the manufacturing precision and bonding reliability worsen
Solution Approach 1:
The patent performs preliminary actions by pre-mounting multiple chip structures to the substrate and pre-forming the encapsulant material to surround the chips before final curing. This preliminary arrangement allows for adjustment and optimization of chip positions and orientations while ensuring proper alignment and bonding reliability before the encapsulant sets the final structure.
Solution Approach 2:
The patent introduces an encapsulant material as an intermediary that bonds the multiple chip structures to the substrate and to each other. This encapsulant serves as a mediator that distributes mechanical and thermal stresses uniformly across all chips, improving bonding reliability and reducing the risk of individual chip failure while enabling complex multi-functional integration.
3Device complexity
If the package structure includes multiple chips, then the functional complexity is improved, but the thermal stress and warpage increase
Solution Approach 1:
The patent changes the thermal parameters of the package structure by selecting materials with matched coefficients of thermal expansion (CTE) between the substrate, chips, and encapsulant. This parameter matching reduces differential thermal stress during temperature cycling while maintaining the functional complexity of multiple integrated chips.
Solution Approach 2:
The patent employs composite material structures including a substrate made of one material system, chips made of another, and an encapsulant that combines properties of both. This composite approach allows optimization of thermal stress distribution across the multi-chip structure while maintaining electrical functionality and mechanical integrity under thermal loading.
4Adaptability or versatility
If the package structure is designed with multiple chips, then the versatility is improved, but the coplanarity of conductive bumps deteriorates
Solution Approach 1:
The patent applies local quality by providing individual support and positioning structures for each chip structure on the substrate, ensuring that each chip maintains its proper orientation and position. This localized support system preserves the coplanarity of conductive bumps across all chips while allowing the overall package to achieve high versatility through multi-functional integration.
Solution Approach 2:
The patent addresses coplanarity issues by introducing a third dimension through the encapsulant material that fills the spaces between and around the chips, providing mechanical support and stress distribution in the vertical dimension. This dimensional approach allows horizontal coplanarity of conductive bumps to be maintained while accommodating vertical variations in chip heights and positions.
Data Source
AI summary
A chip package structure is provided. The chip package structure includes a wiring substrate having a first conductive pad. The chip package structure includes a chip structure over the wiring substrate. The chip package structure includes an antiwarpage structure over the wiring substrate. The antiwarpage structure surrounds the chip structure. The chip package structure includes a first anchor structure on the first conductive pad of the wiring substrate and adjacent to a first lower portion of the antiwarpage structure. The first lower portion is between the first anchor structure and the chip structure, and the first anchor structure and the first conductive pad are electrically insulated from the chip structure.