Chip Area Binning for Timing-Critical Circuit Optimization
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Solution Overview
Problem
Existing electronic circuit design methods are computationally expensive and inefficient in performing area reduction, particularly in timing-critical regions, due to the large number of non-timing-critical cells that need to be optimized, which inhibits the application of timing optimizations.
Innovation Solution
A method and system that divide the chip area into bins, identify placement-congested and timing-critical bins, and perform area reduction on non-timing-critical cells within these bins, using a grid-based approach to compute bin density and criticality scores, and adjust slack thresholds to target specific regions for area recovery, thereby reducing computational expense and enabling timing optimizations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If area reduction is performed on all non-timing-critical cells in the design, then total circuit area is reduced, but computational expense increases significantly
Solution Approach 1:
The design is divided into multiple bins representing different physical regions of the chip. Each bin is independently analyzed for placement congestion and timing criticality, allowing area reduction to be performed selectively on specific bins rather than uniformly across the entire design. This segmentation enables the methodology to focus computational resources on regions where area reduction is most beneficial.
Solution Approach 2:
The patent applies different optimization strategies to different bins based on their specific characteristics. Bins are identified as placement-congested and timing-critical based on local metrics, and area reduction is applied locally to these specific bins rather than globally. This local approach reduces computational expense by avoiding analysis of bins that do not require optimization.
2Speed
If timing optimizations are applied to timing-critical cells, then circuit speed is improved, but placement space is consumed
Solution Approach 1:
The patent performs area reduction on non-timing-critical cells in placement-congested bins before applying timing optimizations to timing-critical cells. This preliminary action creates additional placement space by removing or relocating non-critical cells, ensuring that subsequent timing optimizations have the necessary space to be applied without being constrained by placement congestion.
3Area of stationary object
If area reduction is applied uniformly across the design, then total area is reduced, but timing-critical regions may lack sufficient placement space
Solution Approach 1:
The patent identifies specific bins as placement-congested and timing-critical based on local analysis of cell density and timing metrics. Area reduction is applied selectively to these identified bins rather than uniformly across the entire design. This local approach ensures that timing-critical regions receive appropriate placement space while non-critical regions undergo area reduction, maintaining timing closure.
Data Source
AI summary
A method and system of designing an electronic circuit includes dividing a chip area of a design into a plurality of bins, identifying a candidate bin in the plurality of bins, and performing an area reduction on the candidate bin.