Chip Arrangement With Embedded Interconnects
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Solution Overview
Problem
Current multi-chip packages face inefficiencies and high costs due to restrictions in standard interconnect technologies like wire-bonding, leading to poor electrical and thermal performance, and serial manufacturing processes.
Innovation Solution
A chip arrangement featuring a laminated package with redistribution layers on multiple sides, encapsulated with foils, and metal carriers with vias, allowing for parallel processes in assembly, such as foil lamination and via production, to enhance electrical and thermal connectivity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If wire-bonding is used for interconnection, then standard packaging technologies can be applied, but electrical and thermal performance deteriorates
Solution Approach 1:
The patent extracts the interconnection function from traditional wire-bonding and relocates it to conductive portions formed directly on the insulating material. This allows standard packaging to be used while achieving superior electrical and thermal performance through direct metal-to-metal contact via through-conductors, eliminating the performance limitations of wire-bonding.
Solution Approach 2:
The patent introduces an insulating material with embedded conductive portions as an intermediary structure. This mediator enables both standard packaging compatibility and enhanced electrical/thermal connectivity by providing direct conduction paths through the insulating material, replacing the indirect wire-bonding approach.
2Ease of manufacture
If serial processes are used for manufacturing, then standard assembly procedures can be followed, but productivity decreases
Solution Approach 1:
The patent applies preliminary action by pre-forming conductive portions within the insulating material before chip assembly. This allows multiple chips to be interconnected simultaneously in parallel processes, dramatically improving productivity compared to serial wire-bonding operations performed one chip at a time.
Solution Approach 2:
The patent merges multiple manufacturing operations into a single integrated structure. The insulating material with embedded conductors is prepared in advance, allowing simultaneous assembly and interconnection of multiple chips in parallel, combining what would otherwise be separate serial steps into one efficient process.
3Ease of manufacture
If multiple single-chip packages are assembled separately, then standard packaging technologies can be used, but device complexity increases
Solution Approach 1:
The patent merges multiple single-chip packages into a single integrated multi-chip module. Chips are mounted on a common insulating substrate with shared conductive interconnects, reducing the complexity of assembling and managing multiple separate packages while maintaining compatibility with standard packaging technologies.
Solution Approach 2:
The insulating material serves multiple functions simultaneously: it provides electrical insulation, mechanical support for chip mounting, and houses embedded conductive portions for interconnection. This multi-functionality reduces device complexity by consolidating what would otherwise require separate components and assembly steps.
Data Source
AI summary
A chip arrangement is provided. The chip arrangement includes: a first chip electrically connected to the first chip carrier top side; a second chip electrically connected to the second chip carrier top side; and electrically insulating material configured to at least partially surround the first chip carrier and the second chip carrier; at least one electrical interconnect configured to electrically contact the first chip to the second chip through the electrically insulating material; one or more first electrically conductive portions formed over and electrically contacted to at least one of the first chip carrier top side and second chip carrier top side, and one or more second electrically conductive portions formed over and electrically contacted to at least one of the first chip carrier bottom side and second chip carrier bottom side.