Chip Arrangement With Redistributing Interconnects For Stacking Yield
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Solution Overview
Problem
The challenge in achieving high yield and low manufacturing cost in chip stacking processes, particularly for wide I/O memory stacks, due to issues like non-uniform interconnect heights, missing interconnects, inaccurate placement, and misalignment, which lead to unreliable electrical coupling between logic and memory chips.
Innovation Solution
The implementation of a chip arrangement with a redistribution structure that provides multiple interconnects for each contact, allowing for backup electrical connections and improved alignment, coupled with the use of fuses to select functional signal paths, ensuring reliable coupling and increased yield.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If a large number of interconnects are used to achieve higher bandwidth, then data transfer capability is improved, but manufacturing reliability deteriorates due to increased sensitivity to placement errors and alignment issues
Solution Approach 1:
The patent divides the interconnect structure into multiple segments: first interconnects extend from first contacts through the substrate, second interconnects extend from second contacts, and conductive regions provide additional connection paths. This segmentation creates multiple independent electrical pathways, so that if one interconnect fails due to placement or alignment errors, alternative paths remain available to maintain electrical coupling between chips.
Solution Approach 2:
The patent modifies the geometric parameters of the interconnect structure by extending interconnects in multiple directions (first and second opposite directions) and creating conductive regions at strategic locations. This changes the spatial distribution and connectivity parameters, transforming a single-path configuration into a multi-path network that tolerates placement variations.
2Ease of manufacture
If non-uniform interconnect heights and placement errors occur, then manufacturing complexity is reduced, but electrical connection reliability deteriorates
Solution Approach 1:
The patent incorporates redundant conductive regions and multiple interconnect paths before the bonding process occurs. These redundant elements serve as pre-established backup pathways that cushion against the effects of non-uniform interconnect heights and placement errors, ensuring that electrical connections remain reliable even when manufacturing tolerances are exceeded.
Solution Approach 2:
The conductive regions act as intermediary elements between the first and second interconnects, providing additional connection points and alternative current paths. These intermediaries facilitate electrical coupling even when direct interconnect-to-interconnect alignment is imperfect, mediating the connection reliability issue.
3Reliability
If precise alignment and high-accuracy bonding are required, then electrical coupling reliability is improved, but manufacturing cost increases
Solution Approach 1:
By segmenting the interconnect system into multiple independent pathways (first interconnects, second interconnects, and conductive regions), the patent reduces the stringency of alignment requirements for each individual connection. This segmentation allows standard bonding processes to achieve sufficient reliability without requiring expensive high-precision equipment or processes.
Solution Approach 2:
The conductive regions serve as intermediary connection points that reduce the precision requirements for direct interconnect alignment. By providing additional connection nodes, these intermediaries allow the system to achieve reliable electrical coupling with less stringent alignment tolerances, thereby reducing manufacturing cost.
Data Source
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AI summary
A chip arrangement may include: a first chip including a first contact, a second contact, and a redistribution structure electrically coupling the first contact to the second contact; a second chip including a contact; and a plurality of interconnects electrically coupled to the second contact of the first chip, wherein at least one interconnect of the plurality of interconnects electrically couples the second contact of the first chip to the contact of the second chip.