Semiconductor Chip Assemblage Handling via Carrier Substrate
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Solution Overview
Problem
The handling of individual semiconductor chips in conventional press pack cells is difficult due to loose placement, which complicates electrical connections and mechanical stability, necessitating a method to facilitate chip assembly and connection.
Innovation Solution
The method involves cohesively and electrically conductively connecting semiconductor chips to conductive compensation laminae, using connecting layers such as solder or adhesive, and embedding them in a dielectric compound, with a control electrode interconnection structure to enable efficient electrical connections between chips and secure mechanical bonding.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If semiconductor chips are pressed loosely between contact pieces, then the assembly process is simple, but handling and electrical connection become difficult
Solution Approach 1:
Multiple semiconductor chips are mounted together on a common carrier substrate to form a chip assemblage, merging multiple handling operations into a single unit. This allows the chips to be handled as one integrated component rather than individually, resolving the contradiction between simple assembly and difficult handling.
Solution Approach 2:
A carrier substrate is introduced as an intermediary component that holds multiple chips in a fixed arrangement. This mediator enables both simple assembly (by providing a unified mounting platform) and easy handling (by allowing the entire assemblage to be manipulated as one unit).
2Manufacturing precision
If individual chips are handled separately, then each chip can be positioned precisely, but the overall assembly process becomes complex and time-consuming
Solution Approach 1:
Multiple chips are pre-mounted on the carrier substrate in their final positions before the carrier is installed in the press pack cell. This preliminary action allows precise positioning to be achieved during the initial mounting phase, while subsequent assembly steps become simpler and faster, resolving the contradiction between precision and productivity.
Solution Approach 2:
The assembly process is segmented into distinct phases: first mounting multiple chips on a carrier substrate with precise positioning, then installing the entire carrier assemblage as one unit. This segmentation allows precision work to be done on a manageable scale while maintaining overall assembly efficiency.
3Device complexity
If chips are directly connected to contact plates, then electrical connection is straightforward, but thermal expansion mismatch causes damage
Solution Approach 1:
A dielectric compound is introduced as an intermediary between the chips and the environment, providing mechanical support and electrical insulation while accommodating thermal expansion differences. This mediator allows straightforward electrical connections to be made while protecting against thermal stress, resolving the contradiction between connection simplicity and thermal reliability.
Solution Approach 2:
The chip assemblage uses a composite structure combining semiconductor chips, carrier substrate, and dielectric compound. This composite material approach allows each component to be optimized for its specific function while working together to resolve thermal expansion compatibility issues without complicating the overall connection structure.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach simplifies the handling and connection of semiconductor chips, enhancing mechanical stability and electrical conductivity, while reducing the risk of damage from thermal expansion mismatch between chips and contact plates.
Implementation Method 1
connecting layers (31, 32) composed of solder or adhesive
Implementation Method 2
connecting layers (31, 32) composed of solder or adhesive
Implementation Method 3
The chip assemblies are cohesively connected by means of a dielectric embedding compound
Data Source
AI summary
One aspect of the invention relates to a method for producing a chip assemblage. Two or more chip assemblies are produced in each case by cohesively and electrically conductively connecting an electrically conductive first compensation lamina to a first main electrode of a semiconductor chip. A control electrode interconnection structure is arranged in a free space between the chip assemblies. Electrically conductive connections are produced between the control electrode interconnection structure and control electrodes of the semiconductor chips of the individual chip assemblies. The chip assemblies are cohesively connected by means of a dielectric embedding compound.