Chip Assembly Optical Interconnects Vertical Substrate Integration
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Solution Overview
Problem
Current chip assembly configurations face challenges in providing high-bandwidth, low-latency, low-power, and cost-effective communication due to pin-count limitations, signal degradation, and thermal management issues, especially in next-generation multi-processor architectures, where optical interconnects are needed but consume valuable space and increase latency.
Innovation Solution
A chip assembly configuration with a substrate having short-length transmission lines and a conversion mechanism that converts electrical signals to optical signals, allowing for high-speed communication using optical interconnects while minimizing real estate and thermal management challenges, by positioning the conversion mechanism on the opposite side of the integrated circuit and using short vias to maintain signal integrity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If optical interconnects are used to provide high bandwidth communication, then communication bandwidth is improved, but real estate consumption increases
Solution Approach 1:
The patent positions optical sources and detectors on opposite sides of the substrate, utilizing the third dimension (vertical spacing) to separate optical components from electrical circuitry. This dimensional separation allows optical interconnects to achieve high bandwidth while minimizing lateral space consumption on the substrate surface.
Solution Approach 2:
The patent integrates optical sources and detectors within the substrate structure itself, nesting them between the first and second surfaces. This nesting approach incorporates optical interconnect functionality without adding external components that would consume additional real estate.
2Productivity
If optical interconnects are used to provide high bandwidth communication, then communication bandwidth is improved, but distance between components increases
Solution Approach 1:
By placing optical sources and detectors on opposite sides of the substrate rather than adjacent on the same side, the patent creates direct optical pathways through the substrate thickness. This vertical arrangement minimizes the optical path length compared to lateral routing, reducing component distance while maintaining high bandwidth.
3Productivity
If optical interconnects are used to provide high bandwidth communication, then communication bandwidth is improved, but thermal management difficulty increases
Solution Approach 1:
The patent separates optical components (sources and detectors) from the integrated circuit by positioning them on opposite sides of the substrate. This segmentation isolates heat-generating optical components from sensitive electrical circuitry, simplifying thermal management while preserving high bandwidth communication capabilities.
Solution Approach 2:
The substrate acts as an intermediary barrier between optical components and the integrated circuit. This intermediate structure provides thermal isolation, allowing optical interconnects to operate at high bandwidth without directly transferring heat to the electrical circuitry.
4Productivity
If pin count is increased to provide high bandwidth communication, then communication bandwidth is improved, but pin-count constraints are worsened
Solution Approach 1:
The patent replaces traditional electrical pin-based interconnects with optical interconnects using sources and detectors. This substitution eliminates the need for high pin counts, as optical channels can provide equivalent or superior bandwidth with fewer connection points, thereby reducing device complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enables high-speed communication at data rates greater than 10 Gbps with reduced power consumption and increased component density, addressing the limitations of existing electrical interconnects and optical interconnect implementations.
Implementation Method 1
a conversion mechanism positioned adjacent to the second surface and electrically coupled to the second connectors that converts electrical signals from the integrated circuit into corresponding first optical signals and that converts second optical signals to the integrated circuit into corresponding second electrical signals
Data Source
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AI summary
A chip assembly configuration includes an substrate with an integrated circuit on one side and a conversion mechanism on the other side. The integrated circuit and the conversion mechanism are electrically coupled by a short electrical transmission line through the substrate. Moreover, the conversion mechanism converts signals between an electrical and an optical domain, thereby allowing high-speed communication between the integrated circuit and other components and devices using optical communication (for example, in an optical fiber or an optical waveguide).