Chip Assembly Layout for RF Thermal Control and De-Sense Mitigation

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Solution Overview

Problem

Electronic devices face challenges in meeting thermal and electrical requirements while avoiding de-sense issues, particularly in RF modules, with a need for chip assemblies that balance heat dissipation, electrical performance, and cost-effectiveness.

Innovation Solution

A chip assembly design that includes a first chip and a heat-conducting element with specific area and projection ratios, integrated with a wave-absorbing material and shielding cover, to manage thermal and electrical interference while maintaining a compact form factor.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Temperature

If the area ratio of the heat-conducting element to the chip is increased to improve heat dissipation, then thermal management performance is improved, but electrical performance deteriorates due to de-sense issues in RF modules

Engineering Contradiction:
Improveheat dissipation performanceVSAvoidelectrical performance
Core Design Contradiction:
TemperatureVSReliability

Solution Approach 1:

The patent applies parameter changes by precisely controlling the area ratio of the heat-conducting element to the chip area within the range of 0.1 to 0.85, and the projection area ratio within 0.1 to 0.95. This quantitative parameter optimization resolves the contradiction by finding the optimal balance point where sufficient heat dissipation is achieved while maintaining electrical performance and avoiding de-sense issues in RF modules.

Inventive Principle:
Principle #35Parameter changes

2Temperature

If thermal management measures are strengthened to meet heat dissipation requirements, then temperature control is improved, but electromagnetic interference increases affecting RF module performance

Engineering Contradiction:
Improvetemperature controlVSAvoidelectromagnetic interference
Core Design Contradiction:
TemperatureVSObject-generated harmful factors

Solution Approach 1:

The patent applies local quality by implementing differentiated area ratios for heat-conducting elements at different locations on the chip. The first heat-conducting element has an area ratio of 0.1 to 0.85, while the second heat-conducting element has an area ratio of 0.1 to 0.65. This localized optimization allows effective heat dissipation at each location while controlling overall electromagnetic interference to maintain RF module performance.

Inventive Principle:
Principle #3Local quality

3Ease of manufacture

If the chip assembly design is simplified to reduce cost, then manufacturing cost is reduced, but thermal management capability is insufficient

Engineering Contradiction:
Improvemanufacturing costVSAvoidthermal management capability
Core Design Contradiction:
Ease of manufactureVSTemperature

Solution Approach 1:

The patent applies universality by designing heat-conducting elements that simultaneously serve multiple functions: thermal conduction for heat dissipation, electromagnetic shielding for interference protection, and structural support for chip assembly stability. This multi-functionality allows the chip assembly to achieve adequate thermal management without adding separate specialized components, thereby controlling manufacturing costs.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The design effectively dissipates heat, reduces electromagnetic interference, and maintains electrical performance, achieving a balance between thermal management and cost-effectiveness.

Implementation Method 1

The first heat-conducting element includes a first heat inflow surface having a first heat-conducting area

Methodology Applied
Scientific EffectHeat conduction: Conduction (thermal)

Data Source

PatentUS20250372477A1Chip assembly and electronic device
Publication Date: 2025.12.04 WISTRON NEWEB CORP
  • US20250372477A1 patent drawing
  • US20250372477A1 patent drawing
  • US20250372477A1 patent drawing

AI summary

A chip assembly includes a first chip and a first heat-conducting element. The first chip includes a first chip surface, which has a first chip area. The first heat-conducting element includes a first heat inflow surface, which has a first heat-conducting area. The first heat inflow surface is connected to the first chip surface, and an area ratio of the first heat-conducting area to the first chip area is less than 0.85.