Semiconductor Chip Back Face Interconnects for Wiring Flexibility
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Solution Overview
Problem
Conventional chip-on-chip (CoC) semiconductor devices face performance limitations due to limited wiring resources and flexibility in interconnect formation on the motherboard, which restricts the arrangement of interconnects and adversely affects device performance.
Innovation Solution
The proposed semiconductor device configuration includes a first semiconductor chip, a second semiconductor chip with an expansion portion, and a wiring board, where the second chip is smaller and connected to the wiring board through interconnects on its back face and the expansion portion, increasing the wiring resource and flexibility in interconnect formation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If the conventional CoC semiconductor device configuration is used with a motherboard, then the device structure is simple, but the wiring resource is limited and interconnect formation flexibility is insufficient
Solution Approach 1:
The invention segments the interconnect formation by creating distinct interconnect structures: solder electrodes on the motherboard for power supply, and separate interconnects on the chip back face for signal transmission. This segmentation allows independent optimization of each interconnect type, increasing overall wiring resource and flexibility without significantly complicating the overall device structure.
Solution Approach 2:
The invention utilizes the back face of the chip as an additional dimension for interconnect formation. By forming interconnects on the chip back face and connecting them to the motherboard, the patent creates a three-dimensional interconnect architecture that significantly increases wiring resources without expanding the chip's planar area.
2Adaptability or versatility
If interconnects are arranged on the motherboard to correspond to chip functions, then the wiring resource increases, but the motherboard has limited wiring resource and flexibility
Solution Approach 1:
Instead of arranging all interconnects on the motherboard as in conventional designs, the invention inverts the approach by forming signal interconnects on the chip back face and connecting them to the motherboard. This reversal allows the chip itself to provide the wiring resource, overcoming the motherboard's limited wiring capacity while simplifying the manufacturing process.
3Area of stationary object
If the second chip is larger than the first chip with projecting peripheral portion, then the connection area to motherboard increases, but the device size and thickness increase
Solution Approach 1:
The invention utilizes the vertical dimension by forming interconnects on the back face of the chip. This allows the chip to maintain a compact planar size while providing sufficient connection area through the third dimension (chip thickness), thereby reducing overall device size and thickness without sacrificing connection capacity.
Data Source
AI summary
A semiconductor device includes: a first semiconductor chip; a second semiconductor chip placed such that a front face of the second semiconductor chip faces a front face of the first semiconductor chip, and being smaller in size than the first semiconductor chip; an expansion portion extending outward from at least one side face of the second semiconductor chip; a wiring board placed such that a front face of the wiring board faces the front face of the first semiconductor chip and a back face of the second semiconductor chip; and a first interconnect formed on the back face of the second semiconductor chip and a back face of the expansion portion, and being in connection to the wiring board.