Electronic Chip Backside Attack Protection via Deep Insulating Walls
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Solution Overview
Problem
Electronic chips, such as bank card chips, are vulnerable to hacker attacks that aim to determine the chip's operation and extract confidential information, with existing protection methods being insufficient in detecting attacks from the rear face and requiring improvement in detection thresholds and circuit simplicity.
Innovation Solution
The electronic chip design incorporates alternately arranged P-type and N-type semiconductor bars with detection contacts and a resistance detection circuit, featuring insulating walls that extend deeper than the isolation trenches, ensuring that any attempt to dig a cavity from the rear face increases resistance, triggering an alert and preventing further attack.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If isolation trenches are used to separate circuit elements, then circuit elements are isolated, but the protection depth is insufficient against rear-face attacks
Solution Approach 1:
The patent extends protection from the traditional planar isolation trenches into the vertical dimension by adding insulating walls that penetrate deeper into the semiconductor substrate. This dimensional extension creates multiple barriers (trenches + walls) at different depths, effectively blocking rear-face attack paths while maintaining circuit isolation functionality.
Solution Approach 2:
The isolation structure is segmented into two distinct components: isolation trenches at the surface level and insulating walls extending deeper into the substrate. This segmentation allows each component to perform its specific function - trenches provide surface-level isolation while walls provide deep-level protection against rear-face attacks, creating a multi-layered defense system.
2Reliability
If detection circuits monitor resistance of each box, then attack detection is achieved, but the detection circuit complexity increases
Solution Approach 1:
The patent merges the detection function across multiple boxes by connecting detection contacts of adjacent boxes to a shared detection circuit. Instead of implementing separate detection circuits for each box, the combined approach monitors resistance changes across multiple boxes simultaneously, reducing overall circuit complexity while maintaining comprehensive attack detection capability.
3Area of stationary object
If the pitch between P and N wells is reduced to less than 5 μm, then chip area is reduced, but manufacturing precision requirements increase
Solution Approach 1:
The patent applies different structural qualities to different regions: in the critical attack-prone regions, insulating walls are extended deeper into the substrate to provide enhanced protection, while in other regions, standard isolation structures are maintained. This localized enhancement provides targeted protection without requiring uniform high-precision manufacturing across the entire chip.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design significantly enhances protection against hacker attacks by ensuring that even partial cavity digging is detected, preventing unauthorized access to chip components and maintaining confidentiality, while maintaining chip area and manufacturing simplicity.
Implementation Method 1
Each resistance detection circuit is connected to the two detection contacts of each second bar and is adapted to detect the resistance of each second bar
Data Source
Figure 1A~1B
Figure 2A~2B
Figure 3~5
AI summary
The invention relates to an electronic chip comprising: a plurality of first semiconductor bars of a first type of conductivity and second semiconductor bars of a second type of conductivity arranged alternately and contiguously on a region (3) of the first type of conductivity; two sensing contacts (17) disposed at the ends of each second bar; a resistance sensing circuit (19) between the sensing contacts of each second bar; isolation trenches (11) extending in the second bars to a first depth between circuit elements; and isolation walls (32) extending across the entire width of each second bar to a second depth greater than the first depth.