Structured Chip Backside Interconnect for Small-Pitch Emitters
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Solution Overview
Problem
Existing semiconductor chip interconnection technologies face challenges in achieving uniform thermal and electrical connection with small pitch distances, which are necessary for improved performance and image quality, especially in applications like augmented and virtual reality glasses.
Innovation Solution
A semiconductor chip with a structured bottom side featuring connection pads configured for electrical and thermal connection, allowing for close pitch distances between emitter regions, eliminating the need for wire bonds and enabling improved heat dissipation and current distribution across multiple radiation-emitting regions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of moving object
If conventional interconnection technologies are used, then electrical and thermal connection can be achieved, but pitch distances between emitter regions cannot be sufficiently reduced
Solution Approach 1:
The patent transitions from planar interconnection to three-dimensional vertical interconnection by positioning connection pads on the back side of the semiconductor chip directly beneath the emitter regions. This dimensional change allows electrical and thermal paths to be established vertically through the substrate, enabling small pitch distances between emitters while maintaining uniform connection through the substrate thickness rather than relying on lateral routing that would require larger spacing.
Solution Approach 2:
The patent introduces an intermediary substrate structure that serves as a common platform for multiple emitter regions. The substrate with integrated connection pads acts as a mediator that provides uniform electrical and thermal connection to multiple emitters simultaneously, eliminating the need for individual wire bonds to each emitter and enabling close pitch distances while maintaining connection uniformity.
2Ease of manufacture
If wire bonds are used for electrical connection, then electrical connection can be established, but device complexity and manufacturing difficulty increase
Solution Approach 1:
The patent merges the electrical connection function and thermal connection function into a single integrated substrate structure with connection pads. This consolidation eliminates the need for separate wire bonds and simplifies the interconnection architecture, making the device easier to manufacture with reduced complexity in the interconnection structure.
Solution Approach 2:
The patent extracts the interconnection function from the emitter regions themselves and relocates it to a dedicated substrate layer with connection pads. This separation allows the emitters to be optimized for their primary function while the substrate handles all electrical and thermal interconnection, simplifying both emitter design and manufacturing processes.
3Temperature
If conventional interconnection methods are used, then electrical connection is achieved, but thermal dissipation is insufficient
Solution Approach 1:
The patent designs the substrate connection pads to serve multiple functions simultaneously: electrical connection, thermal conduction, and mechanical support. This multi-functionality allows the same structural element to handle both electrical signals and heat dissipation, improving thermal management without adding separate components that would increase device complexity.
Solution Approach 2:
The substrate acts as an intermediary thermal management system, providing a low-thermal-resistance path from the emitter regions through the connection pads to the package or heat sink. This intermediary structure efficiently conducts heat away from multiple emitter regions, improving overall thermal dissipation and reducing power loss.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution enables reduced power dissipation, increased Wall-plug Efficiency (WPE), improved image quality, and reduced power consumption, while allowing for faster switching times and smaller form factors, making it suitable for applications requiring high current performance and precise optical control.
Implementation Method 1
The structured chip bottom side has connection pads which are configured for the electrical connection of the emitter regions
Implementation Method 2
The structured chip bottom side is configured to electrically and thermally connect the semiconductor chip
Data Source
AI summary
A semiconductor chip with a structured chip back side is specified, the chip back side being configured for electrical and thermal linking of the semiconductor chip, the semiconductor chip having emitter regions configured for producing electromagnetic radiation and the structured chip back side having connection pads configured for electrical linking of the emitter regions. The connection pads are p-contacts or n-contacts, with, in a plan view, all connection pads (which are configured either as p-contacts or as n-contacts overlapping with at least two of the emitter regions in each case and each of these connection pads being configured for electrical linking of only one of the emitter regions. Moreover, a component is specified, in particular comprising at least one such semiconductor chip.