Chip Bonding Layers With Segmented Alignment Marks for Void-Free Stacking
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Solution Overview
Problem
Existing semiconductor packages face challenges in integrating multiple chips with high capacity and miniaturization, particularly in controlling dishing during planarization processes and reducing voids during direct bonding, which affect yield and reliability.
Innovation Solution
A semiconductor package design that includes a first and second semiconductor chip with bonding layers featuring alignment structures composed of external and internal marks, ensuring flat surfaces and precise alignment through controlled dishing and erosion, and direct bonding without adhesive films or connecting bumps.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If a planarization process is performed on the bonding layer to achieve a flat surface, then the surface flatness is improved, but dishing occurs on the alignment structure reducing manufacturing precision
Solution Approach 1:
The alignment structure is divided into multiple segments: external marks on the bonding layer surface and internal marks within the insulating layer. This segmentation allows the planarization process to focus on the bonding layer without significantly affecting the alignment marks, as the internal marks are protected within the insulating layer while external marks provide surface-level alignment reference.
Solution Approach 2:
The alignment marks are formed in advance within the insulating layer before the bonding layer is applied. This preliminary action ensures that the alignment structure is already in place and protected when the bonding layer undergoes planarization, preventing dishing of the alignment marks during the planarization process.
2Reliability
If adhesive films or connecting bumps are used for bonding chips, then bonding reliability is improved, but device complexity and manufacturing steps increase
Solution Approach 1:
The adhesive film and connecting bump are extracted from the bonding structure, replacing them with a direct bonding layer approach. The bonding layer contains both the alignment marks and the bonding functionality, eliminating the need for separate adhesive films and bumps, thus reducing device complexity while maintaining bonding reliability through direct material bonding.
Solution Approach 2:
The bonding layer is designed to serve multiple functions simultaneously: it provides alignment marks for positioning, acts as the bonding interface for direct chip bonding, and eliminates the need for separate adhesive films. This multi-functionality reduces the overall number of components and simplifies the bonding structure.
3Adaptability or versatility
If multiple chips are integrated into a package for high capacity, then functionality is improved, but void formation during bonding increases reducing yield
Solution Approach 1:
The mechanical bonding system using bumps and adhesive films is replaced with a direct material bonding system. This substitution eliminates the air gaps and voids that form between discrete bonding components, allowing multiple chips to be integrated with minimal void formation and improved bonding reliability.
Data Source
AI summary
A semiconductor package includes a first semiconductor chip including a first substrate and a first bonding layer disposed on the first substrate, and having a flat first outer surface provided by the first bonding layer; and a second semiconductor chip disposed on the first outer surface of the first semiconductor chip, including a second substrate and a second bonding layer disposed on the second substrate, and having a flat second outer surface provided by the second bonding layer and contacting the first outer surface of the first semiconductor chip. The first bonding layer includes a first outermost insulating layer providing the first outer surface, a first internal insulating layer stacked between the first outermost insulating layer and the first substrate, first external marks disposed in the first outermost insulating layer and spaced apart from each other, and first internal marks interlaced with the first external marks within the first internal insulating layer.