Semiconductor Chip Bonding Surfaces with Burr-Containment Trenches
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Solution Overview
Problem
The manufacturing process of semiconductor chips often results in burrs on the insulating layers, which can lead to irregular bonding surfaces and deteriorated bonding characteristics between semiconductor chips, affecting the electrical characteristics and reliability of the semiconductor devices.
Innovation Solution
The process involves using a plasma etching method to lower the level of burrs on the insulating layers, either by exposing them to a plasma etching process or forming trenches on the side surfaces of the semiconductor chips, ensuring that the burrs do not protrude above the surface level, thus creating a flat bonding surface.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If laser grooving process is used to separate insulating layers, then manufacturing efficiency is improved, but burrs are generated on the insulating layer surface
Solution Approach 1:
The patent converts the harmful burrs generated by laser grooving into a beneficial feature by forming trenches around them. The trenches contain the burrs within the scribe lane region, preventing them from affecting the chip bonding surfaces while maintaining the efficiency of the laser grooving process.
Solution Approach 2:
The patent extracts the problematic burrs from the chip surface area by forming trenches that isolate them within the scribe lane regions. This separation removes the harmful effect of burrs on bonding surfaces while preserving the manufacturing efficiency of laser grooving.
2Manufacturing precision
If plasma etching is used to remove burrs, then surface quality is improved, but additional process steps are required
Solution Approach 1:
The patent replaces the need for additional plasma etching or mechanical burr removal processes with a photoresist-based trench formation method. The trenches are formed using standard photolithography and etching processes that are already part of the manufacturing flow, eliminating the need for separate burr removal steps.
3Ease of manufacture
If burrs are left on the insulating layer, then manufacturing process is simpler, but bonding characteristics between chips deteriorate
Solution Approach 1:
The patent segments the chip structure by forming trenches that divide the scribe lane region from the chip area. This segmentation isolates burrs within the trenches in the scribe lane, preventing them from affecting the bonding surfaces while maintaining process simplicity.
Solution Approach 2:
The trenches act as an intermediary structure that mediates between the burrs generated by laser grooving and the chip bonding surfaces. The trenches provide a physical barrier that prevents direct contact between burrs and bonding surfaces, preserving bonding characteristics without requiring burr removal.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach improves the bonding characteristics and reliability between semiconductor chips, enhancing the electrical performance and surface quality of the semiconductor devices by preventing burrs from interfering with the bonding process.
Implementation Method 1
performing a plasma process so that a burr according to the laser grooving process protrudes a height that is below a level of front surfaces of a plurality of insulating layers
Data Source
AI summary
A semiconductor device may include a substrate, one or more front pads disposed on a front surface of the substrate, and a circuit layer including an insulating layer and at least one interconnection electrically connected to the one or more front pads. In some embodiments, the circuit layer may be disposed between the one or more front pads and the substrate. In some embodiments, a side surface of the circuit layer may include a burr that protrudes a height that is below a level of a front surface of the circuit layer. Additionally or alternatively, the burr may form a step portion in the circuit layer.