Semiconductor Chip Bonding Interface with Asymmetrical Dielectric Layers

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Solution Overview

Problem

Existing semiconductor packages face challenges in achieving reliable bonding between semiconductor chips due to limitations in bonding strength and thermal history, particularly in the context of miniaturization and high-performance systems-in-package (SiP) technologies.

Innovation Solution

The semiconductor package employs an asymmetrical bonding structure with insulating bonding layers of different materials, such as silicon oxide, silicon nitride, and silicon oxycarbonitride, formed under varying deposition temperatures to enhance dielectric-to-dielectric bonding strength and reduce thermal history.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If conventional bonding methods are used for semiconductor chips, then the bonding process is simple, but the bonding strength and reliability are insufficient

Engineering Contradiction:
Improvebonding strengthVSAvoidbonding structure complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent applies asymmetry by creating an asymmetrical bonding structure where the first bonding pad has different dimensions than the second bonding pad. Specifically, the first bonding pad has a first width and the second bonding pad has a second width that is different from the first width, creating an intentional asymmetrical configuration that enhances bonding strength while maintaining manufacturability

Inventive Principle:
Principle #4Asymmetry

Solution Approach 2:

The patent applies local quality by using different insulating materials for the first and second insulating bonding layers. The first insulating bonding layer includes a first insulating material while the second insulating bonding layer includes a second insulating material that is different from the first insulating material, optimizing local properties at each bonding interface to improve overall reliability

Inventive Principle:
Principle #3Local quality

2Reliability

If insulating bonding layers of different materials are used, then bonding strength is improved, but manufacturing complexity increases

Engineering Contradiction:
Improvebonding strengthVSAvoidmanufacturing complexity
Core Design Contradiction:
ReliabilityVSEase of manufacture

Solution Approach 1:

The patent applies parameter changes by varying the material composition of the insulating bonding layers. The first insulating bonding layer and second insulating bonding layer use different insulating materials with different properties, allowing optimization of bonding strength while the asymmetrical pad design provides additional degrees of freedom for process control

Inventive Principle:
Principle #35Parameter changes

3Reliability

If bonding pads are made asymmetrical with different widths, then bonding reliability is enhanced, but manufacturing precision requirements increase

Engineering Contradiction:
Improvebonding interface reliabilityVSAvoiddimensional control precision
Core Design Contradiction:
ReliabilityVSManufacturing precision

Solution Approach 1:

The patent applies asymmetry by intentionally designing the first bonding pad and second bonding pad with different widths. The first bonding pad has a first width and the second bonding pad has a second width that is different from the first width, creating an asymmetrical bonding interface that enhances reliability while the design accommodates manufacturing tolerances

Inventive Principle:
Principle #4Asymmetry

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach improves bonding strength and reliability, allowing for stable connections between semiconductor chips while minimizing thermal stress, thus enhancing the performance and durability of the semiconductor package.

Implementation Method 1

enhance dielectric-to-dielectric bonding strength

Methodology Applied
Scientific EffectDielectric-to-dielectric bonding:

Data Source

PatentUS12438064B2Semiconductor package with bonding interface
Publication Date: 2025.10.07 SAMSUNG ELECTRONICS CO LTD
  • US12438064B2 patent drawing
  • US12438064B2 patent drawing
  • US12438064B2 patent drawing

AI summary

A semiconductor package includes a first semiconductor chip including a first semiconductor layer, a first through-electrode that penetrates through the first semiconductor layer, a first bonding pad connected to the first through-electrode, and a first insulating bonding layer, and a second semiconductor chip on the first semiconductor chip and including a second semiconductor layer, a second bonding pad bonded to the first bonding pad, and a second insulating bonding layer bonded to the first insulating bonding layer, wherein the first insulating bonding layer includes a first insulating material, the second insulating bonding layer includes a first insulating layer that forms a bonding interface with the first insulating bonding layer and a second insulating layer on the first insulating layer, the first insulating layer includes a second insulating material, different from the first insulating material, and the second insulating layer includes a third insulating material, different from the second insulating material.