Chip Stacked Bonding Structure With Low-k Channels for RC Delay

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Solution Overview

Problem

The reduction of interconnection spacing in chip stacked structures increases parasitic capacitance, leading to increased RC delay and reduced signal transmission performance.

Innovation Solution

Incorporating channels with a dielectric constant less than the dielectric constant of the dielectric layer between adjacent bonding devices, reducing parasitic capacitance and RC delay.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If interconnection spacing is reduced to increase interconnection density, then bandwidth and power consumption are improved, but parasitic capacitance increases leading to increased RC delay and reduced signal transmission performance

Engineering Contradiction:

Improveinterconnection densityVSAvoidsignal transmission performance

Core Design Contradiction:

ProductivityVSReliability

Solution Approach 1:

The patent introduces air gaps (low dielectric constant regions) specifically in the regions between adjacent bonding devices where parasitic capacitance is generated. This local modification of dielectric properties reduces the parasitic capacitance in critical areas without affecting other parts of the chip structure, thereby resolving the RC delay issue while maintaining high interconnection density

Inventive Principle:

Principle #3Local quality

Solution Approach 2:

The patent changes the dielectric constant parameter of the material between bonding devices by introducing air gaps. The air gaps have a dielectric constant of approximately 1, which is significantly lower than conventional dielectric materials. This parameter change directly reduces the parasitic capacitance formula C = εA/d, thereby reducing RC delay and improving signal transmission performance

Inventive Principle:

Principle #35Parameter changes

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

Improves signal transmission performance by minimizing capacitance and RC delay in chip stacked structures.

Implementation Method 1

parasitic capacitance generated between the two adjacent bonding devices has increasingly greater impact on the chip

Methodology Applied

Scientific EffectParasitic capacitance: Capacitance

Implementation Method 2

a dielectric constant of the channel is less than a dielectric constant of a material of the first dielectric layer

Methodology Applied

Scientific EffectDielectric constant: Dielectric Permittivity

Data Source

PatentUS20260018545A1Chip, Chip Stacked Structure, Chip Package Structure, and Electronic Device

Publication Date: 2026.01.15 HUAWEI TECH CO LTD

AI summary

A chip includes a die; and a first dielectric layer disposed on a side of the die, and a plurality of bonding devices that penetrate the first dielectric layer. The plurality of bonding devices include a first bonding device and a second bonding device that are adjacent to each other, a channel between the first bonding device and the second bonding device is formed at the first dielectric layer, and a dielectric constant of the channel is less than a dielectric constant of a material of the first dielectric layer.