Chip Bonding Alignment Marks With Dummy Pad Coverage Matching
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Solution Overview
Problem
In semiconductor devices, existing bonding techniques face challenges in accurately aligning and bonding chips due to issues with overpolishing and dishing during chemical mechanical polishing (CMP), which can lead to gaps or improper joining of semiconductor chips.
Innovation Solution
The semiconductor device incorporates alignment marks and dummy pads with matching coverage on the bonding surfaces, allowing for precise alignment and bonding by ensuring the alignment marks and dummy pads have the same coverage, preventing overpolishing and dishing, and facilitating better chip bonding.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If chemical mechanical polishing (CMP) is used to polish the bonding surface, then the surface flatness is improved, but overpolishing and dishing occur leading to gaps or improper joining of chips
Solution Approach 1:
The patent applies local quality by creating a non-uniform pad structure with different heights. The third pad has a different height than the first and second pads, which prevents overpolishing and dishing in specific critical areas while maintaining overall surface flatness. This localized variation in pad height ensures reliable chip bonding by preventing excessive material removal at critical bonding locations.
Solution Approach 2:
The patent implements preliminary action by pre-forming the multi-height pad structure before the CMP process. The pads are configured with different heights in advance to control the polishing behavior, ensuring that critical areas are protected from overpolishing before the actual polishing occurs. This preliminary structural arrangement prevents dishing and maintains bonding reliability.
2Measurement precision
If alignment marks are made larger or more prominent to improve alignment accuracy, then alignment precision is improved, but the alignment marks become more susceptible to overpolishing and dishing
Solution Approach 1:
The patent applies local quality by providing different pad heights in different regions. Alignment marks are positioned on pads with specific heights that protect them from overpolishing, while other areas have different pad heights to control overall polishing behavior. This localized differentiation maintains alignment mark integrity while ensuring adequate alignment precision.
Solution Approach 2:
The patent implements preliminary action by pre-configuring the pad height structure before polishing. The alignment marks are placed on pads that are formed with appropriate heights in advance, protecting them from overpolishing during the CMP process. This preliminary structural preparation ensures that alignment marks maintain their integrity and dimensional accuracy.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables more accurate and reliable bonding of semiconductor chips, preventing gaps and ensuring proper alignment, leading to improved chip stacking and device performance.
Implementation Method 1
issues with overpolishing and dishing during chemical mechanical polishing (CMP)
Data Source
AI summary
There is provided a semiconductor device including a first chip and a second chip bonded to the first chip. The first chip includes a first alignment mark provided in a first region of a bonding surface and a plurality of first dummy pads provided in a second region of the bonding surface different from the first region. The second chip includes a second alignment mark provided on the bonding surface corresponding to the first alignment mark and a plurality of second dummy pads provided in a region of the bonding surface different from the second alignment mark. A coverage of the first alignment mark in the first region is substantially the same as the coverage of the first dummy pads in the second region.