Chip-to-Chip Bonding Misalignment Detection Patterns

Resolve Bottlenecks,
Find Innovative SolutionsGenerate Solutions

Solution Overview

Problem

Semiconductor memory devices face misalignment failures during chip-to-chip bonding, leading to reduced contact area and increased resistance, which existing technologies struggle to detect effectively, affecting product reliability and manufacturing efficiency.

Innovation Solution

Incorporating misalignment detection patterns and circuits on both memory and circuit chips, which are shorted to each other when misalignment exceeds a preset value, allowing for the detection of misalignment failures through a test pad, enabling early detection and prevention of faulty device fabrication.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Volume of moving object

If chip-to-chip bonding is performed to reduce device size, then device size is reduced, but misalignment failure occurs during bonding

Engineering Contradiction:

Improvedevice sizeVSAvoidbonding reliability

Core Design Contradiction:

Volume of moving objectVSReliability

Solution Approach 1:

The patent applies preliminary action by forming misalignment detection patterns on chips before bonding occurs. These patterns are positioned to detect potential misalignment issues prior to actual bonding, allowing for early identification and correction of alignment problems that would otherwise compromise bonding reliability while enabling the continued use of chip-to-chip bonding for size reduction

Inventive Principle:

Principle #10Preliminary action

2Difficulty of detecting and measuring

If misalignment detection patterns are added to detect bonding issues, then detection capability is improved, but device complexity increases

Engineering Contradiction:

Improvemisalignment detection capabilityVSAvoidchip structure complexity

Core Design Contradiction:

Difficulty of detecting and measuringVSDevice complexity

Solution Approach 1:

The patent employs copying by creating simplified detection patterns that replicate the essential alignment relationship between bonded chips. Rather than implementing complex detection systems, the invention uses copied geometric patterns (such as bridge patterns or pad patterns) that can be easily fabricated and evaluated, providing effective misalignment detection while minimizing additional device complexity

Inventive Principle:

Principle #26Copying

Solution Approach 2:

The misalignment detection patterns function as disposable test structures that serve their purpose during bonding verification and can be intentionally designed to fail or be removed after serving their detection function. This approach provides reliable detection capability without permanently increasing the operational complexity of the device

Inventive Principle:

Principle #27Cheap short-living objects (Disposable)

Data Source

PatentUS11049776B2Semiconductor memory device having chip-to-chip bonding structure

Publication Date: 2021.06.29 SK HYNIX INC

AI summary

A semiconductor memory device includes a first chip having a first pad and a first misalignment detection pattern on a first surface; and a second chip having a second pad and a second misalignment detection pattern on a second surface, and bonded to the first surface of the first chip such that the second pad is coupled with the first pad. The second chip includes a misalignment detection circuit which is coupled between the second misalignment detection pattern and a test pad and outputs a first voltage provided from the first misalignment detection pattern, to the test pad, in the case where a misalignment between the first chip and the second chip exceeds a preset value such that the first misalignment detection pattern and the second misalignment detection pattern are shorted to each other.