Chip Bonding Pad Circuitous Traces Impedance Matching
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Solution Overview
Problem
Conventional flat panel displays require increased numbers of FPC boards and extended control circuit boards due to higher signal transmission impedances, leading to higher material costs and area occupation, which complicates signal transmission and increases costs.
Innovation Solution
The design incorporates circuitous traces for the first and second wires, allowing for individually adjustable transmission impedances and parallel connections of conductive layers in the chip bonding pad, reducing the number of FPC boards and control circuit board area, while ensuring equivalent signal transmission levels across driving chips.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the number of FPC boards and control circuit board area are increased to enable all driving chips to receive signals at equivalent levels, then signal transmission quality is improved, but material costs and device complexity increase
Solution Approach 1:
The patent adjusts the transmission impedance parameters of individual wires by making some traces circuitous rather than straight. This allows each wire's impedance to be individually tuned to achieve equivalent signal levels at all driving chips, eliminating the need for additional FPC boards or larger control circuit boards.
Solution Approach 2:
The patent applies different trace configurations to different wires based on their specific impedance requirements. Some wires have circuitous traces while others have straight traces, creating local variations in transmission characteristics to achieve overall signal balance without increasing system complexity.
2Manufacturing precision
If circuitous traces are used for first and second wires to individually adjust transmission impedances, then signal transmission impedance matching is improved, but wire layout complexity increases
Solution Approach 1:
The transmission impedance of each wire is precisely controlled by adjusting the trace configuration. Circuitous traces increase the effective length and alter the impedance characteristics, allowing each wire to be individually matched to its required impedance value for optimal signal transmission.
Solution Approach 2:
The patent uses circuitous (curved) traces instead of straight lines for some wire connections. These curved paths allow for increased trace length within a compact area, enabling impedance matching without proportionally increasing the overall wire length or occupying excessive space.
3Reliability
If parallel connections of conductive layers are implemented in chip bonding pad, then transmission impedance is reduced, but manufacturing complexity increases
Solution Approach 1:
The patent combines multiple conductive layers (first, second, and third conductive layers) into a single chip bonding pad structure with parallel connections. This merging of multiple conductive paths reduces the overall transmission impedance by providing multiple simultaneous current paths, while the integrated structure manages manufacturing complexity.
Solution Approach 2:
The chip bonding pad uses a composite structure with multiple conductive layers separated by dielectric layers. This layered composite architecture allows for reduced transmission impedance through parallel conduction paths while maintaining manufacturability through standardized multi-layer PCB fabrication techniques.
Data Source
AI summary
A flat panel display and a chip bonding pad thereof are provided. The flat panel display includes a display panel, an FPC board, first and second source driving chips, and a control circuit board. First and second wires in a peripheral circuit region of the display panel extend from the underneath of the FPC board to two opposite sides of the display panel and electrically connect the FPC board. The first source driving chips electrically connect the FPC board through parts of the first wires. The second source driving chips electrically connect the FPC board through the second wires. The chip bonding pad is under one of the first and second source driving chips. The chip bonding pad includes a first dielectric layer having first through holes and a second dielectric layer having second and third through holes arranged alternately. The second through holes correspond to the first through holes.