Multi-Core Chip Boot Sequence With Priority Queues
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Solution Overview
Problem
Current chip starting methods for multi-core and multi-channel processors are inadequate in ensuring robustness and performance, particularly due to the lack of structural optimization, which can lead to chip failure if a flash channel experiences issues during the initialization process.
Innovation Solution
A chip starting method that sets a first priority queue for processors and a second priority queue for storage units, where the first processor with the highest priority loads the start program from each storage unit, and the process continues until successful loading or failure across all units, with a boot controller managing the sequence and reporting success or failure to adjust the loading sequence.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a single flash channel is used for storing start programs in multi-core processors, then the device complexity is reduced, but the reliability deteriorates because flash channel failures cause chip failure
Solution Approach 1:
The patent divides the storage system into multiple independent flash channels (at least two channels), where each channel can independently store and provide start programs for processors. This segmentation ensures that a failure in one channel does not affect the other channels, thereby improving reliability while maintaining manageable complexity through modular architecture
Solution Approach 2:
The patent implements redundant storage of start programs across multiple flash channels and processors, creating a backup mechanism before failures occur. When a flash channel or processor fails, the system can immediately switch to alternative sources without causing chip failure, thus cushioning against potential reliability issues
2Productivity
If all processors attempt to load start programs simultaneously from multiple storage units, then the productivity is improved, but the device complexity increases due to coordination requirements
Solution Approach 1:
The patent establishes a predetermined loading sequence for processors based on priority levels before the actual loading process begins. The boot controller pre-configures which processor loads from which storage unit first, eliminating the need for complex real-time coordination during the loading process itself. This preliminary arrangement enables faster parallel loading while keeping the control mechanism simple
Solution Approach 2:
The patent implements a dynamic loading mechanism where the boot controller can adjust the loading sequence and assign different priorities to processors based on their startup status and storage unit availability. This dynamic approach allows the system to optimize loading efficiency in real-time without requiring complex static coordination structures
Data Source
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AI summary
A chip starting method, a multi-core processor chip and a storage medium. The chip starting method comprises: setting a first starting priority for more than two processors, and separately setting, for each processor, a second priority of starting each storage unit in more than two storage units; determining, according to the first priority, a first processor that is to be started and has the highest priority; the first processor successively loading a start program from each storage unit according to the second priority corresponding to the first processor, and executing the start program to perform an initialization operation; ending program loading of the first processor when loading of the start program from any storage unit in the more than two storage units succeeds, or loading of the start program from all storage units in the more than two storage units fails; and starting program loading of the second processor and so on until program loading of the more than two processors is completed.