Chip Bridge Package Structure for Compact High-Speed Interconnects
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Solution Overview
Problem
Conventional chip manufacturing technologies face challenges in creating high-speed and small-volume interconnections between chips, which are necessary for large-scale integrated circuits, and existing packaging methods are complex and difficult to operate.
Innovation Solution
A package structure and packaging method that utilize a chip bridge with a frontside and backside, where the backside is bonded to a substrate, and a redistribution layer with interconnect vias and metal layers that electrically connect the chip bridge, first chip, and chip structure, simplifying the packaging process by avoiding the need to lift the chip bridge with an uneven frontside.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a silicon bridge chip is embedded in a silicon substrate to interconnect chips, then heterogeneous chip packaging is achieved, but the packaging structure becomes more complicated
Solution Approach 1:
The packaging structure is divided into distinct functional layers: substrate layer, chip bridge layer, redistribution layer, and chip layer. Each layer performs a specific function and can be manufactured and tested independently, reducing overall packaging complexity while maintaining heterogeneous integration capability
Solution Approach 2:
The chip bridge serves as an intermediary component between the substrate and the chips. It provides a standardized interface that simplifies the connection between heterogeneous chips, allowing different chip types to be interconnected through a common bridge structure rather than requiring complex direct bonding
2Speed
If conventional packaging methods are used to achieve high-speed interconnections, then chip interconnection is possible, but the interconnection volume is large and speed is limited
Solution Approach 1:
The interconnection architecture transitions from traditional lateral routing to a multi-layer vertical stacking approach. The redistribution layer with multiple interconnection layers enables signals to travel through the vertical dimension, reducing lateral interconnection length and volume while increasing transmission speed
Solution Approach 2:
Multiple interconnection layers are nested within the redistribution layer structure, with interconnect vias penetrating through metal layers. This nested arrangement allows multiple signal paths to be packed into a compact vertical space, reducing overall interconnection volume while maintaining high-speed capabilities
3Ease of manufacture
If the chip bridge frontside is uneven after bonding, then bonding can be completed, but the chip bridge cannot be easily lifted for subsequent processing
Solution Approach 1:
The substrate is bonded to the chip bridge frontside before the chip bridge is fully processed. This preliminary bonding action provides mechanical support and stability, allowing subsequent processing steps to be performed without needing to lift the chip bridge, thereby eliminating the operational difficulty caused by uneven surfaces
Solution Approach 2:
The bonding process creates a replicated interface between the substrate and chip bridge that maintains structural integrity. The bonding layer acts as a copy or transfer medium that allows the chip bridge to be securely attached without requiring manual handling or lifting, preserving ease of operation throughout subsequent manufacturing steps
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution enables efficient electrical connections between chips and substrates, reduces the overall height of the package structure, and improves packaging integration by using solder pads and a redistribution layer to connect the chip bridge and first chip, making the packaging method simpler and easier to operate.
Implementation Method 1
solder pads between the frontside of the chip bridge and the substrate and electrically connecting the chip bridge with the redistribution layer
Implementation Method 2
conductive bumps between the redistribution layer and the first chip, and between the redistribution layer and the chip structure, the conductive bumps electrically connecting the first chip with the redistribution layer, and the conductive bumps also electrically connecting the chip structure and the redistribution layer
Implementation Method 3
a backside of the chip bridge is bonded to a substrate
Data Source
AI summary
A package structure includes a substrate; a chip bridge including a frontside and a backside that is bonded to the substrate; a redistribution layer bonded to the frontside of the chip bridge and including one or more stacked interconnection layers, an interconnection layer including an interconnect via and an interconnection metal layer on the interconnect via, and the interconnect via being in contact with the chip bridge; solder pads between the frontside of the chip bridge and the substrate and electrically connecting the chip bridge with the redistribution layer; a first chip bonded to the redistribution layer and electrically connected to the chip bridge; and a chip structure bonded to the redistribution layer on a side of the first chip along a lateral direction, the chip structure being electrically connected to the redistribution layer, and also electrically connected to the first chip through the chip bridge.