Drive Circuit Chip Bump Alignment for Flat-Panel Display Mounting

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Solution Overview

Problem

The existing methods for mounting drive circuit chips on flat-panel display devices suffer from misalignment issues due to the positional displacement between alignment marks and gold bumps, leading to decreased mounting accuracy and subsequent deterioration of display quality.

Innovation Solution

The solution involves configuring the conductive layers between the semiconductor substrate and alignment bumps to be within the profile of the alignment bumps, preventing them from influencing the recognition of the bump's position, and ensuring that the conductive layers do not project beyond the profile of the alignment bumps, thus facilitating accurate alignment and mounting.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If the conductive layer profile is set larger than the gold bump profile to ensure electrical connection, then the electrical connection reliability is improved, but the position measurement accuracy of the gold bump deteriorates due to the conductive layer influencing the photographed pattern

Engineering Contradiction:
Improveelectrical connection reliabilityVSAvoidposition measurement accuracy of gold bump
Core Design Contradiction:
ReliabilityVSMeasurement precision

Solution Approach 1:

The invention divides the bumps into two distinct types: alignment bumps and output bumps. Alignment bumps are specifically designed with conductive layers that do not project from the bump profile, optimizing them for position measurement. Output bumps have conductive layers that project from the profile, ensuring reliable electrical connection. This segmentation allows each bump type to be optimized for its specific function without compromise.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The invention applies different structural characteristics to different locations on the drive circuit chip. At locations where alignment bumps are needed, the conductive layer is configured to be within the bump profile. At locations where output bumps are needed, the conductive layer projects from the bump profile. This local differentiation allows the system to simultaneously achieve high measurement precision and high electrical connection reliability where needed.

Inventive Principle:
Principle #3Local quality

2Ease of manufacture

If alignment marks are used for mounting the drive circuit chip, then the mounting process is simplified, but misalignment occurs due to positional displacement between the alignment mark and the gold bump

Engineering Contradiction:
Improvemounting process simplicityVSAvoidmounting accuracy
Core Design Contradiction:
Ease of manufactureVSManufacturing precision

Solution Approach 1:

The invention makes the alignment bumps themselves serve as the alignment reference, eliminating the need for separate alignment marks. By using the alignment bumps' own positions as the reference points for mounting, the system achieves both ease of manufacture (using existing bump structures) and high manufacturing precision (no positional displacement between separate marks and bumps).

Inventive Principle:
Principle #25Self-service

Solution Approach 2:

The alignment bumps serve multiple functions: they provide the alignment reference for mounting, ensure accurate position measurement, and maintain electrical connection reliability. This multi-functionality eliminates the need for separate alignment marks while maintaining mounting simplicity and improving mounting accuracy simultaneously.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Data Source

PatentUS7679189B2Display device and manufacturing method of the same
Publication Date: 2010.03.16 MAGNOLIA PURPLE CORP
  • US7679189B2 patent drawing
  • US7679189B2 patent drawing
  • US7679189B2 patent drawing

AI summary

A display device includes a drive circuit chip, and a substrate on which the drive circuit chip is mounted. The drive circuit chip includes a semiconductor substrate, an insulation layer, a first conductive layer and a second conductive layer formed of metal between the semiconductor substrate and the insulation layer, and a first bump and a second bump formed over the insulation layer. The first bump is superposed with the first conductive layer, and a profile of the first bump in plan view is within a profile of the first conductive layer in plan view. The second bump is superposed with the second conductive layer, and a profile of the second pump in plan view is beyond a profile of the second conductive layer in plan view.