Semiconductor Chip Bump Layout for Adhesion Reliability
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The arrangement form of bumps on semiconductor chips affects the reliability of the adhesive layer attachment process and subsequently the reliability of the semiconductor package, which is not adequately addressed by existing technologies.
Innovation Solution
A semiconductor chip design with varying bump densities in different regions, including a central region and peripheral regions with alternating high and low bump densities, enhancing adhesion reliability during the adhesive layer attachment process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If uniform bump density is used across the entire chip, then manufacturing process is simple, but adhesion reliability of the adhesive layer is insufficient
Solution Approach 1:
The patent applies local quality by dividing the chip surface into different regions (first, second, third, and fourth regions) with different bump densities. The first and second regions have a first bump density while the third and fourth regions have a second bump density that is higher than the first. This localized variation in bump density optimizes adhesion reliability in different areas of the chip without requiring complete redesign of the entire bump pattern.
2Reliability
If higher bump density is used throughout the chip, then adhesion reliability improves, but manufacturing complexity and cost increase
Solution Approach 1:
The patent changes the parameter of bump density across different regions of the chip. Specifically, the first and second regions use a lower bump density while the third and fourth regions use a higher bump density. This parameter variation allows the chip to achieve reliable adhesion in critical areas while maintaining manufacturability and avoiding the complexity associated with uniformly high bump density across the entire chip surface.
Data Source
AI summary
A semiconductor chip that includes a chip body that has a first side surface, a second side surface, a third side surface, and a fourth side surface; a central region at a central portion of the chip body; and a peripheral region at a peripheral portion of the chip body and adjacent to at least one of the first side surface to the fourth side surface, wherein the peripheral region includes a first unit region that includes a plurality of first bumps of a first bump density, and a second unit region that includes a plurality of second bumps of a second bump density higher than the first bump density.