Semiconductor Chip Bump Layout for Warpage-Resistant Lead Bonding
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Solution Overview
Problem
In semiconductor packages, lead misalignment and separation occur due to substrate distortion and warpage during thermal compression bonding, especially with reduced bump pitch and multiple rows of bumps, leading to bonding issues.
Innovation Solution
Designing bumps with varying lengths and arrangements on a chip to increase bonding strength, with longer bumps having larger bonding areas to resist strain and stress from substrate warpage, preventing lead shifting and misalignment.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If bumps are arranged with multiple rows and reduced pitch to increase connection density, then electrical connectivity is improved, but substrate distortion and warpage cause lead misalignment and bonding failure
Solution Approach 1:
The patent applies local quality by creating different bump lengths at different locations on the chip. Specifically, bumps in the second direction have varying lengths where outer bumps are longer than inner bumps, and bumps in the first direction have varying lengths where bumps at certain positions are longer than others. This local differentiation compensates for substrate warpage and distortion at specific areas, ensuring reliable bonding across the entire chip surface while maintaining high connection density.
Solution Approach 2:
The patent changes the physical parameter of bump length to address bonding reliability. By varying the length of bumps in different directions and positions, the bonding area between bumps and leads is adjusted. Longer bumps provide larger bonding areas that can accommodate substrate distortion and warpage, preventing lead misalignment and bonding failure while maintaining the reduced pitch arrangement for high connectivity.
2Ease of manufacture
If uniform bumps are used across the chip, then manufacturing is simplified, but substrate warpage causes lead separation and bonding misalignment
Solution Approach 1:
Instead of uniform bumps, the patent implements local quality by creating bumps with different lengths at different positions. The chip includes bumps of at least two different lengths, with longer bumps positioned at locations more susceptible to substrate warpage and distortion. This localized differentiation maintains manufacturing feasibility while significantly improving bonding alignment precision under thermal stress.
Solution Approach 2:
The patent applies beforehand cushioning by pre-designing bumps with extended lengths in anticipation of substrate warpage and distortion. The longer bumps are positioned strategically to provide additional bonding area that can absorb the effects of thermal expansion and substrate deformation during the bonding process, preventing lead separation and misalignment before they occur.
3Strength
If bumps with larger bonding area are used, then bonding strength is increased, but chip area is consumed
Solution Approach 1:
The patent applies local quality by varying bump lengths only in specific directions and positions where substrate warpage and distortion occur, rather than increasing bump size uniformly across the entire chip. This selective approach increases bonding strength at critical locations while minimizing the overall chip area consumption, as bumps in other areas maintain their original dimensions.
Solution Approach 2:
The patent changes the length parameter of bumps in specific directions (first and second directions) rather than increasing all dimensions uniformly. By extending only the length of bumps in directions affected by substrate distortion, the bonding area is increased where needed to improve bonding strength, while the width and other dimensions remain unchanged, thus conserving chip area.
Data Source
AI summary
A semiconductor package includes a flexible circuit board and a chip which includes a first bump group and a second bump group. First bumps of the first bump group and second bumps of the second bump group are provided to be bonded to leads on the flexible circuit board. The second bumps are designed to be longer than the first bumps in length so as to increase bonding strength of the second bumps to the leads, prevent the leads from being shifted and separated from the first and second bumps and prevent lead bonding misalignment.