Semiconductor Chip Buried Insulating Layer Polishing
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Solution Overview
Problem
Current methods for fabricating System in Package (SiP) semiconductor devices face challenges in achieving high packaging density and stable patterning of semiconductor chips with varying thicknesses, as high viscous resins are required for thick insulating layers, leading to difficulties in exposure and pattern formation, limiting the ability to mount chips of different thicknesses.
Innovation Solution
A semiconductor device and fabrication method where semiconductor chips are mounted on a substrate with projected electrodes, and an insulating layer is formed and polished to expose the electrodes, allowing for fine pad electrode formation and connection to upper wiring layers, enabling the use of non-photosensitive resins and accommodating chips of varying thicknesses.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If a thick insulating layer is formed to bury a thick semiconductor chip, then the chip can be properly embedded, but high viscous resin is required which causes difficulty in exposure and patterning
Solution Approach 1:
The insulating layer formation process is segmented into multiple steps: first forming a base insulating layer, then adding a resin layer for embedding the semiconductor chip, and finally forming a photosensitive resin layer for patterning. This segmentation allows each layer to have optimized properties - the base layer provides thickness, the resin layer embeds the chip, and the photosensitive layer enables easy patterning without requiring high viscosity throughout the entire insulating structure.
Solution Approach 2:
Different regions of the insulating structure have different material properties optimized for their specific functions. The base insulating layer uses non-photosensitive resin for thickness and chip embedding, while the top patterning layer uses photosensitive resin for easy exposure and pattern formation. This local differentiation resolves the contradiction between needing thick insulating layers and maintaining ease of patterning.
2Volume of moving object
If the amount of exposure is increased to expose thick resin insulating film, then the thick film can be exposed, but pattern crush occurs and stable patterning becomes difficult
Solution Approach 1:
The exposure process is segmented by applying it only to the thin photosensitive resin layer on top, rather than attempting to expose the entire thick insulating structure. This allows standard exposure amounts to be used, preventing pattern crush while still achieving the desired patterning effect in the critical top layer where patterns are formed.
Solution Approach 2:
The photosensitive property is localized to the top patterning layer rather than being present throughout the entire thick insulating film. This local photosensitivity allows precise patterning with standard exposure conditions, avoiding the pattern crush that would occur if the entire thick structure required high exposure amounts.
3Adaptability or versatility
If semiconductor chips of different thicknesses are buried in a common resin insulating layer, then packaging versatility is improved, but focal depth differs in exposure making high resolution openings difficult to form
Solution Approach 1:
The insulating structure is segmented into a thick base layer for embedding chips of various thicknesses and a thin top photosensitive layer for precise patterning. This segmentation allows the base layer to accommodate thickness variations while the thin top layer maintains consistent focal depth for high-resolution exposure and opening formation, regardless of the underlying chip thickness variations.
Solution Approach 2:
The photosensitive functionality is localized to a thin top layer that maintains uniform thickness and focal depth, while the underlying non-photosensitive base layer provides the thickness accommodation for different chip types. This local differentiation enables both versatility in chip thickness and precision in pattern formation.
4Ease of manufacture
If photosensitive resin is used for the insulating layer, then patterning is easier, but expensive materials are required
Solution Approach 1:
The insulating structure is segmented into a large-volume non-photosensitive resin base layer and a thin photosensitive resin top layer. This segmentation allows the expensive photosensitive resin to be used only where needed for patterning (minimizing material cost), while the bulk of the insulating structure uses cheaper non-photosensitive resin, thus resolving the contradiction between patterning ease and material cost.
Solution Approach 2:
The photosensitive property is applied locally only to the thin top patterning layer rather than throughout the entire insulating structure. This local application provides patterning ease where required while minimizing the quantity of expensive photosensitive resin used, thus reducing overall material cost while maintaining manufacturing ease for the critical patterning step.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for the creation of SiP devices with improved packaging density and the ability to connect pad electrodes to upper wiring layers, reducing the thickness of semiconductor chips and eliminating the need for expensive photosensitive resins, while maintaining the thickness of the SiP device.
Implementation Method 1
an insulating layer which is formed as the semiconductor chip is buried therein and which is polished from a top surface of the insulating layer to a height at which a top of the projected electrode is exposed
Data Source
AI summary
A semiconductor device and a fabrication method thereof are provided. A semiconductor device which is packaged as it includes a semiconductor in which an electronic circuit is disposed, the semiconductor device including: a substrate; a semiconductor chip which has a semiconductor main body having the electronic circuit formed thereon, a pad electrode formed on the semiconductor main body and a projected electrode that is connected to the pad electrode and projected from a surface of the semiconductor main body, wherein the semiconductor chip is mounted on the substrate from the back side of the surface to form the projected electrode thereon; and an insulating layer which is formed as the semiconductor chip buried therein and is polished from a top surface of the insulating layer to a height at which a top of the projected electrode is exposed.