Electronic Chip Buried Layer Bias Current Detector
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Electronic chips, such as bank card chips, are vulnerable to fault injection attacks where hackers disrupt chip operation using laser pulses or applied potentials, making existing protection methods ineffective and difficult to implement.
Innovation Solution
An electronic chip design featuring a semiconductor substrate with a buried layer and wells of specific conductivity types, including a buried layer bias current detector that generates an alert signal when the bias current exceeds a threshold, triggering countermeasures to stop the attack.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a buried layer with opposite conductivity type is introduced between the substrate and wells, then protection against fault injection attacks is improved, but device complexity increases
Solution Approach 1:
The semiconductor structure is segmented into distinct conductivity-type regions: a first conductivity type substrate, a second conductivity type buried layer, and first conductivity type wells. This segmentation creates multiple pn junctions that block fault injection attacks by preventing direct electrical pathways through the device, while maintaining functional circuit regions within the wells.
Solution Approach 2:
The buried layer with opposite conductivity type acts as an intermediary barrier between the substrate and the wells. This intermediate layer with second conductivity type prevents direct coupling between the substrate and well structures, blocking laser-induced fault injection while allowing the functional circuits in the wells to operate normally.
2Reliability
If thickness of the first well between buried layer and second wells is optimized to 2-3 μm, then protection effectiveness is improved, but manufacturing precision requirements increase
Solution Approach 1:
The thickness of the first well is optimized to a specific parameter range of 2-3 μm. This parameter optimization ensures that the well structure provides adequate protection while maintaining manufacturability. The specific thickness range balances the need for sufficient barrier properties against fault injection with the capabilities of standard semiconductor manufacturing processes.
3Difficulty of detecting and measuring
If a bias current detector is implemented to monitor buried layer current, then detection capability against attacks is improved, but device complexity increases
Solution Approach 1:
The buried layer bias current detector utilizes the existing buried layer structure and its inherent current characteristics to detect attacks. The detector monitors the bias current flowing through the buried layer, which changes when fault injection attacks occur. This self-service approach leverages the device's own operational parameters for detection without requiring completely separate sensing systems.
Solution Approach 2:
The bias current detector provides feedback about the electrical state of the buried layer to the control circuitry. When the detector identifies abnormal current patterns indicative of a fault injection attack, it triggers protective responses such as resetting the device or isolating affected circuits, creating a closed-loop protection system.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Effectively protects electronic chips from fault injection attacks by detecting and responding to abnormal current changes caused by laser pulses or potential applications, ensuring the chip's operation is not disrupted, and preventing unauthorized access to confidential data.
Implementation Method 1
biasing the substrate and the first well to a reference potential; biasing the buried layer so as to block the junction between the buried layer and the substrate and the junction between the buried layer and the first well
Implementation Method 2
a buried layer bias current detector suitable for producing an alert signal when the bias current is, in absolute value, greater than a value comprised between 2 and 50 μA
Data Source
Figure 1~2
Figure 3A~3B
Figure 4
AI summary
The invention relates to an electronic chip, comprising: a semiconductor substrate (46) doped with a first type of conductivity; a buried layer (36) doped with a second type of conductivity covering the substrate; a first box (37) doped with the first type of conductivity covering the buried layer; circuits (10, 24, 32) separate from the buried layer formed in and on the first box and/or in and on second boxes (12, 26, 16) formed in the first box; and a detector of the bias current (I) of the buried layer.