Chip-Mounted Bypass Capacitor Layout for Low Power Impedance
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Solution Overview
Problem
Existing semiconductor devices face challenges in reducing power supply impedance, particularly in high-speed devices like DDR4 SDRAM, due to the cracking of protective films when bypass capacitors are directly soldered onto the chip and increased distance leading to insufficient impedance reduction when connected to a base material.
Innovation Solution
A semiconductor device design where a chip capacitor is mounted on the semiconductor chip via a die attach film, with wires connecting the capacitor to the chip's electrode pads, reducing the length of these wires and thus the power supply impedance, while preventing cracks in the protective film by avoiding direct soldering.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the bypass capacitor is directly soldered onto the semiconductor chip, then the power supply impedance can be reduced, but the protective film covering the main surface of the semiconductor chip may be cracked by the reflow process
Solution Approach 1:
The patent introduces an intermediary mounting structure (elevated region or protruding portion) between the bypass capacitor and the semiconductor chip. This intermediary structure allows the capacitor to be mounted without direct contact with the chip surface, preventing the reflow process from cracking the protective film while still maintaining low power supply impedance through short connection paths.
2Ease of manufacture
If the bypass capacitor is connected with a base material, then the mounting is simplified, but the distance between the power supply terminal and the bypass capacitor becomes long, resulting in insufficient power supply impedance reduction
Solution Approach 1:
The patent utilizes the vertical dimension by creating an elevated region or protruding portion on the semiconductor chip. This allows the bypass capacitor to be mounted closer to the power supply terminal in the vertical direction, reducing the effective electrical distance and impedance without complicating the horizontal mounting process on the base material.
Data Source
AI summary
A semiconductor device includes: a base material having a first terminal; a semiconductor chip having a first electrode pad electrically connected with the first terminal, a second electrode pad to which a power supply potential is to be supplied, and a third electrode pad to which a reference potential is to be supplied, and mounted on the base material via a first member; a chip capacitor having a first electrode and a second electrode, and mounted on the semiconductor chip via a second member; a first wire electrically connecting the first electrode pad with the first terminal; a second wire electrically connecting the second electrode pad with the first electrode without going through the base material; and a third wire electrically connecting the third electrode pad with the second electrode without going through the base material.