Chip Capacitor Fuse Segmentation for Variable Capacitance

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Solution Overview

Problem

Existing chip capacitor designs require individual design and manufacturing for each capacitance value, making it time-consuming and labor-intensive to accommodate multiple capacitance values, and unable to rapidly adjust to changes in equipment specifications.

Innovation Solution

A chip capacitor design featuring a substrate with multiple capacitor elements and fuses that can be disconnected to adjust capacitance values, allowing for a common design to accommodate various capacitance values by selecting and cutting fuses, and forming multilayer capacitor structures for high capacitance in a compact size.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If individual design is performed for each capacitance value, then manufacturing precision is improved, but productivity deteriorates

Engineering Contradiction:
Improvecapacitance value precisionVSAvoiddesign and manufacturing speed
Core Design Contradiction:
Manufacturing precisionVSProductivity

Solution Approach 1:

The capacitor structure is divided into multiple discrete capacitor elements (first, second, third capacitor elements) with different capacitance values. Each element can be independently connected or disconnected through separate fuse structures, allowing the total capacitance to be adjusted by selecting which elements are active. This segmentation enables a single design to produce multiple capacitance values without requiring individual design iterations.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The invention creates a universal capacitor design that can accommodate multiple capacitance values through the use of switchable fuse structures. The same basic capacitor structure with multiple elements and fuse configurations can serve different capacitance requirements, making the design multi-functional and adaptable to various specifications without redesign.

Inventive Principle:
Principle #6Universality (Multi-functionality)

2Adaptability or versatility

If individual design is performed for each capacitance value, then adaptability is improved, but loss of time worsens

Engineering Contradiction:
Improvecapability to accommodate different capacitance valuesVSAvoiddesign period
Core Design Contradiction:
Adaptability or versatilityVSLoss of time

Solution Approach 1:

The capacitor design pre-includes multiple capacitor elements and fuse structures that are prepared in advance during the manufacturing process. The fuse structures are pre-configured to allow selective disconnection of specific capacitor elements. This preliminary preparation enables rapid adaptation to different capacitance requirements simply by cutting or leaving intact specific fuses, without requiring time-consuming redesign or reconfiguration.

Inventive Principle:
Principle #10Preliminary action

3Quantity of substance

If multilayer capacitor structures are formed, then capacitance value is improved, but device complexity worsens

Engineering Contradiction:
Improvetotal capacitanceVSAvoidstructure complexity
Core Design Contradiction:
Quantity of substanceVSDevice complexity

Solution Approach 1:

The invention transitions from a single-layer capacitor structure to a multilayer configuration by stacking multiple capacitor elements vertically or in series/parallel arrangements. This dimensional change allows the accumulation of total capacitance from multiple smaller elements without significantly increasing the horizontal footprint, achieving high capacitance in a compact three-dimensional structure.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Data Source

PatentUS10777360B2Chip capacitor and method for manufacturing the same
Publication Date: 2020.09.15 ROHM CO LTD
  • US10777360B2 patent drawing
  • US10777360B2 patent drawing
  • US10777360B2 patent drawing

AI summary

A chip capacitor and a method for manufacturing the chip capacitor, where the chip capacitor includes a substrate, a first external electrode disposed on the substrate, a second external electrode disposed on the substrate, capacitor elements formed on the substrate and connected between the first external electrode and the second external electrode, and fuses that are formed on the substrate, are each interposed between the capacitor elements and the first external electrode or the second external electrode, and are capable of disconnecting each of the capacitor elements.