Chip Capacitor Solder Joint Reliability on Wiring Substrates
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Solution Overview
Problem
Existing semiconductor devices face reliability issues due to residual solder formation between chip capacitors and solder resist layers during the solder reflow process, leading to potential short circuits and reduced connection reliability.
Innovation Solution
The semiconductor device design features a wiring substrate with specific terminal patterns and solder resist openings that prevent solder paste from penetrating between the capacitor and the solder resist layer, ensuring that the solder paste is contained within designated regions, thereby reducing residual solder formation and enhancing connection reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If solder paste is applied during the solder reflow process, then electrical connection between chip capacitor and wiring substrate is achieved, but residual solder forms between the capacitor and solder resist layer causing short circuits and reliability issues
Solution Approach 1:
The patent applies local quality by creating a specific opening pattern in the solder resist layer that is tailored to the terminal pattern geometry. The opening is designed to expose only the necessary portions of the terminal pattern for solder connection while covering other areas to prevent solder overflow. This localized modification of the solder resist layer allows solder paste to be contained within designated regions, eliminating residual solder formation between the capacitor and solder resist layer while maintaining reliable electrical connections.
Solution Approach 2:
The patent implements preliminary action by pre-configuring the solder resist layer with openings that match the terminal pattern before the solder reflow process. This preliminary design of the opening pattern ensures that when solder paste is applied and reheated, it is automatically contained within the correct areas. The preventive structure is established in advance, stopping residual solder formation before it can cause harmful effects during the soldering process.
2Reliability
If solder paste is contained within designated regions, then residual solder formation is minimized, but the design complexity of terminal patterns and opening portions increases
Solution Approach 1:
The opening pattern is designed with local quality by making it correspond to the specific geometry of the terminal pattern. Rather than using a generic or overly complex design, the opening is tailored to expose only the necessary portions of the terminal pattern for solder connection. This targeted approach achieves reliable solder joint integrity while avoiding unnecessary design complexity, as the opening pattern directly mirrors the functional requirements of the terminal layout.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design effectively minimizes residual solder formation, improving the reliability of semiconductor devices by maintaining the integrity of solder joints and preventing short circuits, thus enhancing overall device performance.
Implementation Method 1
solder reflow process
Data Source
AI summary
The terminal pattern TP1 of the wiring substrate PB has a side T1a facing the terminal pattern TP2 and the terminal pattern TP2 of the wiring substrate PB has a side T2a facing the side T1a of the terminal pattern TP1. The side T1a and the side of T2a are exposed from the opening portion OP1 and OP2 of the solder resist layer SR1 respectively, and outer peripheries of terminal patterns TP1 and TP2 other than sides T1a and T2a are not exposed from opening portions OP1 and OP2. The opening portion OP1 and the opening portion OP2 are separated from each other. The electrode E1 of the capacitor C1 is soldered to the terminal pattern TP1 exposed from the opening portion OP1, and the electrode E2 of the capacitor C1 is soldered to the terminal pattern TP2 exposed from the opening portion OP2.