Chip Capacitor Via Formation and Layer Integration
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Solution Overview
Problem
The existing manufacturing processes for chip capacitors are inefficient and costly, requiring an increase in the number of processing steps with each additional layer, which complicates the production process.
Innovation Solution
A method of manufacturing chip capacitors that involves forming multiple contact vias simultaneously, reducing the number of processing steps despite an increase in the number of conductive and insulating layers, by using a specific configuration of electrodes and dielectric layers with non-overlapping wiring portions and a surface insulating and protective film structure.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If the number of conductive layers and insulating layers is increased to enhance chip capacitor functionality, then the device performance is improved, but the number of manufacturing steps increases proportionally, reducing manufacturing efficiency and increasing costs
Solution Approach 1:
The patent combines the formation of multiple contact vias (first through fourth contact vias) into a single simultaneous manufacturing step. Instead of forming each via separately through sequential photolithography and etching processes, the invention uses a unified process to create all necessary vias through the insulating layers and dielectric layers at once, thereby maintaining manufacturing efficiency while supporting increased device complexity
Solution Approach 2:
The invention addresses the manufacturing complexity issue by transitioning from sequential two-dimensional layer-by-layer processing to a simultaneous three-dimensional via formation approach. Multiple vias are created in parallel through the stacked layers, effectively utilizing the vertical dimension to perform multiple operations in a single process step, thus decoupling device complexity from manufacturing step count
2Device complexity
If the number of processing steps is increased to accommodate additional layers, then the chip capacitor structure complexity is improved, but the manufacturing process becomes more complicated and costly
Solution Approach 1:
The patent merges multiple discrete manufacturing operations into a single integrated process step. Specifically, the formation of first, second, third, and fourth contact vias through different insulating and dielectric layers is combined into one simultaneous etching operation, thereby maintaining process simplicity while achieving the required structural complexity
Solution Approach 2:
The invention employs preliminary patterning and alignment preparations that enable subsequent simultaneous via formation. By pre-configuring the layer structure and alignment marks before the unified via formation step, the patent ensures that complex multi-layer connections can be achieved without proportionally increasing the number of processing steps
Data Source
AI summary
The present disclosure provides a chip capacitor, including: a first capacitor unit formed over a substrate and including a first lower electrode, first dielectric layer and first upper electrode; a second insulating layer over the first capacitor unit; a second conductive layer over the second insulating layer, and includes a first wiring portion and a second wiring portion, the first wiring portion being connected to the first lower electrode by a first contact via and connected to a first pad by a third contact via, the second wiring portion being connected to the first upper electrode by a second contact via and connected to a second pad by a fourth contact via; a first external electrode connected to the first wiring portion; and a second external electrode connected to the second wiring portion.