Chip Card Metallic Core Testing for Eddy Current Damping
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Solution Overview
Problem
Contactless or dual-interface chip cards with metallic core layers face reduced contactless functionality due to electromagnetic damping, leading to shorter switching distances and potential defects from impurities or closures in the slot, resulting in manufacturing costs and quality control issues.
Innovation Solution
A method to test the card body's metallic core layer before integrating the chip module, using a test apparatus to assess the oscillating circuit's quality by exciting it with a Dirac pulse and measuring the decay, ensuring only functional card bodies are used for further manufacturing, thereby reducing rejects and costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Strength
If a metallic core layer is integrated into the card body to improve mechanical strength and service life, then the resistance to torsion and structural robustness are improved, but the contactless function is substantially damped and the switching distance decreases
Solution Approach 1:
The metallic core layer is segmented by introducing a slot that extends from the cavity to an outer edge, dividing the continuous metal structure into separate regions. This segmentation interrupts eddy current paths while maintaining the overall mechanical strength and torsion resistance of the card body.
Solution Approach 2:
The metallic core layer is configured with different properties in different regions: the main body retains full metal coverage for mechanical strength, while the slot region creates localized non-conductive pathways. This allows the card body to have both high structural integrity and improved contactless functionality in critical areas.
2Reliability
If the slot width is increased to effectively prevent eddy current and improve contactless function, then the damping effect is reduced and switching distance increases, but the mechanical stability of the chip card deteriorates
Solution Approach 1:
Instead of creating a wide slot throughout the entire metallic core layer, the slot is implemented partially - extending only from the cavity to an outer edge rather than across the full width. This partial action provides sufficient eddy current interruption to improve contactless function while maintaining mechanical stability.
Solution Approach 2:
The slot dimensions are optimized to specific parameter ranges that balance electromagnetic and mechanical requirements. The slot width and depth are controlled to create effective eddy current disruption while maintaining structural integrity, representing a precise parameter optimization solution.
3Strength
If the slot is made narrow to maintain mechanical stability, then the structural integrity is preserved, but the effectiveness in preventing eddy current is reduced
Solution Approach 1:
The slot is configured with specific dimensional relationships - extending from the cavity to an outer edge in a direction that maximizes eddy current interruption effectiveness. This dimensional configuration ensures that even a narrow slot provides sufficient electromagnetic disruption while maintaining mechanical strength.
Solution Approach 2:
The slot is pre-configured in the metallic core layer before chip module assembly, ensuring proper positioning and dimensions. This preliminary action guarantees that the slot provides adequate eddy current prevention while maintaining mechanical integrity, avoiding the need for post-assembly modifications.
4Measurement precision
If the card body is tested after chip module integration, then defective card bodies are detected, but manufacturing costs increase due to rejected chip modules
Solution Approach 1:
The card body is tested for contactless functionality before chip module integration by temporarily positioning a test chip module. This preliminary action identifies defective card bodies early, preventing waste of chip modules on unsuitable substrates and reducing overall manufacturing costs.
Solution Approach 2:
A test chip module is used as a temporary copy during the testing phase to evaluate card body functionality without committing to final assembly. This allows defect detection while preserving the actual chip module for successful card bodies, optimizing resource utilization.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach ensures only card bodies with suitable metallic core layers are used, enhancing the contactless functionality and reducing manufacturing costs by preventing defective card bodies from progressing to chip module integration, thus improving overall chip card quality and efficiency.
Implementation Method 1
exciting it with a Dirac pulse and measuring the decay
Implementation Method 2
electrons of the metallic core layer move around the chip module along a flow direction, so that an eddy current is created by the movement of the electrons
Implementation Method 3
the energy transmitted by the card reader to the chip card by means of electromagnetic waves is partly absorbed and reflected by the metallic core layer
Implementation Method 4
the energy transmitted by the card reader to the chip card by means of electromagnetic waves is partly absorbed and reflected by the metallic core layer
Implementation Method 5
an intrinsic magnetic field is produced on the other hand, which counteracts a change in the alternating magnetic field it has produced
Data Source
AI summary
A method is provided for testing a card body with a metallic core layer for a contactless or dual-interface chip card, and a method is provided for manufacturing a contactless or dual-interface chip card. The method involves testing the functionality of the card body before the chip module employed for testing, or a corresponding chip module, is fixed into the cavity of the card body. A card body having impurities, a partial closure or full closure in the slot of its metallic core layer fails the test and is not used at all for fixing the chip module and for the subsequent manufacturing steps.