Chip Carrier Layout With Segmented Bonding Openings
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Solution Overview
Problem
The existing chip carrier structures face issues with copper circuit oxidation, leading to delamination of gold-plated protective layers, which reduces the reliability and lifespan of electronic components.
Innovation Solution
A chip carrier structure is designed with a spacer portion at the circuit layer exposed from the solder mask openings, dividing the circuit layer into blocks and reducing the area of the circuit layer and protective layer exposed, thereby minimizing delamination risks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the exposed surface of copper circuits is covered with a gold-plated anti-oxidation layer, then oxidation prevention is improved, but delamination occurs between the gold layer and copper layer due to poor bonding force
Solution Approach 1:
An intermediate layer is introduced between the gold plating layer and the copper circuit layer. This intermediate layer serves as a bonding bridge, improving adhesion between the gold and copper layers while preventing delamination. The intermediate layer has compatible bonding characteristics with both gold and copper, resolving the poor bonding force issue.
Solution Approach 2:
The patent uses a composite structure consisting of multiple layers (copper circuit layer, intermediate layer, and gold plating layer). This composite material approach combines the oxidation resistance of gold with the bonding capabilities of the intermediate layer, achieving both protection and strong adhesion.
2Ease of operation
If continuous and large-area metal (copper) layers are formed in power supply and ground layers, then wiring ease is improved, but the area of exposed circuit layer increases leading to more oxidation and delamination
Solution Approach 1:
The continuous large-area copper layer is segmented by dividing it into multiple smaller regions or patterns. This segmentation reduces the total exposed area while maintaining the electrical connectivity and wiring functionality. The divided structure also reduces stress concentration, preventing delamination.
3Reliability
If the ground layer is placed on the outermost layer of the carrier substrate, then grounding effectiveness is improved, but the exposed copper area increases causing more oxidation and delamination
Solution Approach 1:
The ground layer design applies local quality by creating specific patterns or regions with different properties. The ground layer is configured to provide effective grounding in critical areas while minimizing the exposed copper area in other regions. This localized optimization maintains grounding effectiveness while reducing oxidation and delamination risks.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The implementation of the spacer portion significantly reduces the area of the circuit layer and protective layer exposed, enhancing the reliability and lifespan of the chip carrier structure by minimizing delamination issues.
Implementation Method 1
since the element of copper is also chemically active, it is easily oxidized when exposed to the atmospheric environment, forming copper oxide
Data Source
AI summary
A chip carrier structure is provided and defined with a chip carrier region and a wire bonding region, and the chip carrier structure includes: an insulating layer; a circuit layer formed on the insulating layer; a solder mask layer formed on the insulating layer and the circuit layer and having a plurality of openings in the wire bonding region; and a protective layer formed on a portion of the circuit layer exposed from the solder mask layer, where an area of the protective layer in each of the openings is less than 70000 μm2. By reducing the areas of the circuit layer exposed from the openings and the protective layer exposed from the openings, the problem of delamination caused by poor bonding force between the materials of the protective layer and the circuit layer is greatly reduced, thereby improving the reliability and lifespan of the chip carrier structure.