Chip-to-chip port coherency via link training transitions
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Solution Overview
Problem
Existing network communication systems face challenges in maintaining lane coherency across long haul channels, leading to latency and inefficiencies due to the need for overhead data and complex protocols to identify lane ownership, which disrupts reliable data transmission.
Innovation Solution
The system employs a method where two chips synchronize using a link training protocol, utilizing a uniquely identifiable logic transition in a known data pattern to establish and maintain port coherency during muxing and demuxing operations, eliminating the need for additional control signals or headers, and allowing immediate transition to mission mode without latency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If overhead data is inserted into packet headers to indicate lane ownership, then lane coherency is maintained, but latency increases and processing complexity increases
Solution Approach 1:
The invention extracts the lane coherency function from the data path by using dedicated training sequences transmitted on control lanes during link training. This separates the coherency establishment phase from the data transmission phase, allowing data to flow without overhead without compromising lane identification.
Solution Approach 2:
The invention performs lane coherency establishment in advance during link training before actual data transmission begins. Training sequences are sent beforehand to establish which lanes correspond to which ports, and this information is cached for use during mission mode operation, eliminating the need for per-packet overhead.
2Reliability
If gearbox chips coordinate using proprietary or industry standard protocols to identify lane ownership, then lane coherency is achieved, but device complexity and processing operations increase
Solution Approach 1:
The invention makes the receiving gearbox chip self-sufficient by having it independently identify lane ownership through analyzing training sequences during link training. The receiving chip uses timing logic and known data patterns to autonomously determine which lanes correspond to which ports, without requiring complex proprietary protocols or extensive coordination with the transmitting chip.
3Reliability
If lane training is performed after existing protocol completion during initialization, then lane coherency is established, but bring-up latency increases
Solution Approach 1:
The invention merges the lane training function with the existing link training protocol by incorporating training sequences into the standard link training process. The training sequences are transmitted during the normal link training phase, combining two functions (link establishment and lane coherency) into a single integrated process that completes in one pass.
Data Source
AI summary
A network system includes a first device and a second device coupled to each other that mux and demux data for LSL to HSL transitions. The muxing and demuxing function in the first and second device, respectively, use timing logic from an existing training protocol, such as link training (“LT”). Although LT is used for establishing links between two chips, and has no provision for maintaining port coherency for port-specific input data on one chip to port-specific output data on another chip, the LT does have a uniquely identifiable logic transition in a known data pattern used for LT that can be multi-purposed for syncing the muxing and demuxing of the two interfaced chips, using a predetermined port sequence on both chips to maintain coherency of port-specific data.