Chip-to-Chip Coherency Messaging Without Completion Waits
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Solution Overview
Problem
Existing chip-to-chip communication protocols, such as AMBA-CHI, inefficiently use IO bandwidth and increase power consumption due to unnecessary coherency traffic rules, leading to bottlenecks in high-performance computing systems.
Innovation Solution
Implementing an ordered communication network to transmit chip-to-chip messages without waiting for inter-chip completion responses, ensuring memory coherency by using verification checks to determine if requests have already been sent, and transmitting subsequent messages accordingly.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional C2C communication protocols (e.g., AMBA-CHI) are used to ensure memory coherency, then coherency is maintained, but IO bandwidth is inefficiently used and power consumption increases
Solution Approach 1:
The patent extracts and eliminates unnecessary coherency traffic rules from the communication protocol. By identifying and removing redundant verification steps and completion responses that do not contribute to actual coherency maintenance, the system reduces power consumption while preserving essential coherency functionality through a streamlined protocol.
Solution Approach 2:
The patent applies partial action by implementing coherency checks only when necessary rather than universally. The system determines based on communication context whether full coherency verification is needed, allowing selective execution of coherency maintenance operations to reduce overall power consumption while maintaining reliability where required.
2Reliability
If conventional C2C communication protocols are used to ensure memory coherency, then coherency is maintained, but IO bandwidth is inefficiently used
Solution Approach 1:
The patent removes redundant protocol elements including unnecessary completion responses and verification traffic. By extracting these unnecessary components from the communication protocol, the system reduces the quantity of data transmitted over the IO link while maintaining memory coherency through essential operations only.
Solution Approach 2:
The patent changes the protocol parameters by modifying communication flow characteristics. Instead of synchronous wait-for-completion semantics, the system employs asynchronous communication with selective verification, changing the temporal and data parameters of communication to reduce bandwidth usage while preserving coherency guarantees.
3Reliability
If conventional C2C communication protocols are used to ensure memory coherency, then coherency is maintained, but latency increases
Solution Approach 1:
The patent implements preliminary action by preparing and transmitting messages in advance without waiting for completion responses. The system can send eviction requests and data messages before receiving confirmation from the remote chip, as long as coherency is maintained through subsequent verification mechanisms, thereby reducing latency.
Solution Approach 2:
The patent enables continuous communication by eliminating the stop-and-wait pattern of conventional protocols. Messages can be transmitted continuously without blocking for inter-chip completion responses, maintaining useful action flow while coherency is preserved through selective verification, thus reducing overall latency.
4Reliability
If inter-chip completion responses are waited for before transmitting subsequent messages, then coherency is maintained, but productivity decreases
Solution Approach 1:
The patent allows subsequent messages to be transmitted in advance before receiving completion responses for previous messages. By performing preliminary actions of sending eviction requests and data messages without waiting for prior operations to complete, the system increases communication throughput while maintaining coherency through verification mechanisms.
Solution Approach 2:
The patent enables continuous message transmission without the stop-and-wait pattern that limits productivity in conventional protocols. The system maintains useful action continuity by sending multiple messages in sequence without blocking for completion responses, as long as coherency verification is satisfied, thereby maximizing communication throughput.
Data Source
AI summary
In various examples, when a bridge of a chip has received an eviction request from a client of the chip, the bridge may transmit a read request that corresponds to the same cache line to another chip without waiting for an inter-chip completion response for the eviction request. When the read request is received, the bridge may determine whether the eviction request has already been sent to the other chip and transmit the read request based at least on the eviction request being sent to the other chip using an ordered communication network to ensure the communications are received and/or processed by the other chip in an order that maintains memory coherency. Additionally, the chips may process read unique requests without using an inter-chip completion acknowledgement and may process copy back requests by transmitting corresponding copy back write data with the copy back requests.