Chip Conductive Layer Structure With Wider Vias for Lower Resistance
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Solution Overview
Problem
The challenge of forming reliable semiconductor devices at smaller sizes is exacerbated by the increasing complexity of fabrication processes as feature sizes continue to decrease, leading to difficulties in processing and manufacturing integrated circuits.
Innovation Solution
A chip structure is developed with integrated conductive layers and capacitors that include specific materials and processes, such as high-k dielectric materials and conductive layers, to enhance the formation of capacitors and inductors, reducing resistance and improving charging speed and operation frequency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If feature sizes continue to decrease to increase functional density, then production efficiency increases and costs decrease, but fabrication process complexity increases and reliability decreases
Solution Approach 1:
The patent changes material parameters by introducing high-k dielectric materials (such as hafnium oxide, zirconium oxide) to replace traditional silicon dioxide, thereby achieving higher capacitance density without increasing physical size. This material parameter change allows continued scaling while maintaining performance
Solution Approach 2:
The patent employs composite material structures combining multiple dielectric layers with different k-values, conductive layers with varying resistivities, and barrier/adhesion layers to create optimized capacitor and inductor structures that function reliably at smaller feature sizes
2Productivity
If feature sizes continue to decrease to increase functional density, then production efficiency increases and costs decrease, but manufacturing reliability decreases
Solution Approach 1:
The patent modifies physical parameters by increasing dielectric constant (k-value) through material selection, which compensates for reduced physical dimensions and maintains capacitance values despite smaller feature sizes, thereby ensuring reliable operation
Solution Approach 2:
The patent transitions from planar capacitor structures to vertically stacked three-dimensional capacitor structures, increasing the effective capacitance area without increasing the chip footprint, thus maintaining reliability during scaling
3Length of moving object
If conventional conductive paths are used in scaled-down devices, then device size decreases, but resistance increases and contact area decreases
Solution Approach 1:
The patent implements multi-layer stacked conductive paths in the vertical dimension, creating parallel current flow paths that reduce overall resistance and increase effective contact area without increasing lateral device dimensions
Solution Approach 2:
The patent uses composite conductive structures combining different metal materials (such as copper, cobalt, tungsten) with optimized thicknesses and arrangements to achieve low resistance while maintaining small feature sizes
Data Source
AI summary
A chip structure is provided. The chip structure includes a semiconductor substrate. The chip structure includes a first conductive layer over the first dielectric layer. The chip structure includes a conductive via passing through the first conductive layer and electrically connected to the first conductive layer. The chip structure includes a conductive pad over and in direct contact with the conductive via. The chip structure includes a second conductive layer over and spaced apart from the first conductive layer. The chip structure includes a first dielectric layer conformally covering a second lower portion of a sidewall of the second conductive layer. The chip structure includes a third conductive layer over the first dielectric layer.