On-Chip Configuration Bus Tunneling for Multi-Chip Setup
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Solution Overview
Problem
Existing chip configurations require each chip to have its own interface to the host, consuming physical space and resources, which is inefficient.
Innovation Solution
A mechanism is introduced where a first chip receives configuration requests from the host and tunnels them over an inter-chip data interconnect, such as an Ethernet link, to configure remote chips without requiring direct interfaces on all chips.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If each chip is provided with its own interface to the host for configuration, then configuration capability is ensured, but physical space and resources are consumed excessively
Solution Approach 1:
The host interface logic on the first chip performs multiple functions: it handles both local configuration requests for the first chip itself and forwards remote configuration requests to second chips via the inter-chip data interconnect. This multi-functionality eliminates the need for separate dedicated interfaces on each chip while maintaining comprehensive configuration capability across all chips in the network.
Solution Approach 2:
The first chip acts as an intermediary between the host and second chips for configuration purposes. It receives configuration requests from the host, determines the target chip, and tunnels the configuration settings through the inter-chip data interconnect to the appropriate destination chip, thereby enabling indirect configuration access.
2Ease of operation
If each chip has its own host interface, then direct configuration access is enabled, but system complexity increases
Solution Approach 1:
The patent extracts the host interface functionality from individual chips and consolidates it into a single location (the first chip). By removing redundant interface logic from second chips and routing their configuration access through the first chip, the system reduces overall complexity while maintaining operational simplicity through a unified configuration entry point.
3Reliability
If multiple chips have direct host interfaces, then configuration reliability is improved, but resource consumption increases
Solution Approach 1:
The patent merges the configuration access paths of multiple chips into a single unified path through the first chip. By consolidating configuration requests through one host interface logic instance rather than distributing them across multiple independent interfaces, the system maintains reliable configuration delivery while significantly reducing the quantity of interface resources required.
Data Source
AI summary
A plurality of chips each comprises a respective local chip-configuration control bus (Cbus). When a target chip ID of Cbus request obtained by a first chip matches a chip ID of the first chip, it supplies a target chip-configuration setting, specified by the Cbus request, via the local Cbus of the first chip, to the target chip-configuration register address within the local chip-configuration register address space of the first chip. But when the target chip ID matches a chip ID of a second chip, the first chip causes the Cbus request to be tunnelled over an inter-chip data interconnect to the second chip, where the second chip is configured to supply the tunnelled chip-configuration setting via the respective Cbus of the second chip to the target chip-configuration register address within the chip-configuration register address space of the second chip.