Semiconductor Chip Connection Structure for Thermal Stress Management
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Solution Overview
Problem
Semiconductor packages face issues with crack formation and delamination due to thermal stress at interfaces between materials with different thermal expansion coefficients, particularly in diffusion solder bonds, which are thin and inadequate for stress absorption.
Innovation Solution
A connection structure comprising a stack of electrically conducting layers, including a contact layer for ohmic contact, a mechanical decoupling layer for stress absorption, a diffusion barrier layer to prevent diffusion, and a diffusion solder layer for bonding, with the mechanical decoupling layer positioned between the diffusion barrier and contact layers, allowing for optimized material selection and stress reduction.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Temperature
If a thin diffusion solder bond structure is used, then thermal dissipation is improved and package size is reduced, but stress absorption capability deteriorates
Solution Approach 1:
The bond structure is segmented into multiple functional layers: a contact layer for ohmic contact, a mechanical decoupling layer for stress absorption, a diffusion barrier layer, and a diffusion solder layer. This segmentation allows each layer to be optimized for its specific function, with the mechanical decoupling layer specifically designed to absorb thermal expansion stress while maintaining thin overall structure for thermal dissipation
Solution Approach 2:
The invention uses a composite multi-layer structure combining different materials with complementary properties. The mechanical decoupling layer uses materials optimized for stress absorption, while the diffusion solder layer provides bonding capability. This composite approach enables simultaneous achievement of thin profile for thermal management and adequate stress absorption capability
2Strength
If a buffer layer is positioned directly on the rear side of the semiconductor chip, then mechanical decoupling is provided, but the number of usable metals is limited due to ohmic contact requirements
Solution Approach 1:
The buffer layer function is segmented from the contact function. The mechanical decoupling layer is positioned between the contact layer and the diffusion barrier layer, separating its function from the ohmic contact requirement. This allows independent material selection for each layer based on their respective functional requirements
Solution Approach 2:
The contact layer serves as an intermediary between the semiconductor chip and the mechanical decoupling layer. It provides the necessary ohmic contact to the chip while allowing the mechanical decoupling layer to use materials optimized purely for mechanical stress absorption without being constrained by electrical contact requirements
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This structure effectively absorbs stress, reduces interface stress, and maintains electrical performance by allowing separate optimization of each layer's function, improving mechanical decoupling without compromising thermal dissipation or electrical properties over time.
Implementation Method 1
a contact layer (11) for providing an ohmic contact to a semiconductor chip
Implementation Method 2
at least one mechanical decoupling layer (12) for mechanically decoupling the semiconductor chip and the substrate
Implementation Method 3
stress occurs at the interfaces due to the difference in thermal expansion coefficient between the different materials
Implementation Method 4
at least one diffusion barrier layer for preventing diffusion between the mechanical decoupling layer and an adjacent layer
Implementation Method 5
a diffusion solder layer for providing a diffusion soldered mechanical bond and an electrical connection to a metal substrate
Data Source
AI summary
Connection structure (5) for attaching a semiconductor chip (2) to a metal substrate (4) is provided which has a plurality of electrically conducting layers (11, 12, 13, 14) arranged in a stack. The stack has a contact layer (11) for providing an ohmic contact to a semiconductor chip (2), at least one mechanical decoupling layer (12) for mechanically decoupling the semiconductor chip (2) and the metal substrate (4), at least one diffusion barrier layer (13) and a diffusion solder layer (14) for providing a diffusion soldered mechanical bond and an electrical connection to a metal substrate (4). The mechanical decoupling layer (12) is positioned in the stack between the diffusion barrier layer (13) and the contact layer (11).