Built-in Connection Testing Circuit for Multi-Chip Fault Localization
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Solution Overview
Problem
Current multi-chip package testing methods are inefficient, requiring lengthy test times and high costs due to the difficulty in accurately determining connection faults between chips, which hinders mass production yield and stability.
Innovation Solution
A connection testing apparatus and method using a built-in test circuit with a charge source, charge draining unit, and comparator to test each connection point between substrates by analyzing voltage variations along a current path, allowing for independent and rapid connection testing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional functional testing methods are used to test connection points between chips, then fault coverage can be achieved, but test time is prolonged and test cost increases
Solution Approach 1:
The patent segments the connection testing into individual connection point tests using dedicated test circuits at each connection location. Each test circuit independently tests its specific connection point, allowing parallel testing of multiple connections simultaneously, thereby reducing overall test time while maintaining comprehensive fault coverage.
Solution Approach 2:
The patent introduces test circuits as intermediary elements between the chips being tested. These test circuits include charge sources, charge draining units, and detectors that facilitate connection testing without requiring complex functional test patterns, thus reducing test time and cost while achieving reliable fault detection.
2Reliability
If conventional functional testing methods are used to test connection points between chips, then fault coverage can be achieved, but test cost increases
Solution Approach 1:
The patent implements self-service testing where each chip contains built-in test circuits that automatically test connection points. The test circuits on each chip independently perform testing functions, eliminating the need for complex external test equipment and reducing test costs while maintaining high fault coverage.
Solution Approach 2:
The patent uses simplified test circuit copies at each connection point that replicate the essential testing functionality without requiring full functional test implementations. This copying approach reduces test complexity and cost while achieving the necessary fault coverage through multiple independent test points.
3Ease of operation
If two-chip handshake testing is used, then connection testing can be performed, but it cannot accurately determine which connection fault causes functional faults
Solution Approach 1:
The patent segments the connection interface into individually testable connection points, each with its own test circuit. This segmentation allows precise identification of which specific connection point is faulty, providing detailed fault location information that enables accurate troubleshooting and repair.
Solution Approach 2:
The patent replaces the indirect mechanical handshake testing method with direct electrical measurement using test circuits that include charge sources, charge draining units, and detectors. This substitution provides direct feedback on connection status, enabling accurate determination of fault locations without ambiguity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach simplifies and accelerates connection testing, reduces test costs, and instantly identifies faulty connections, thereby improving mass production yield and stability by enabling precise fault localization and resolution.
Implementation Method 1
by using a voltage variation caused by a current path
Implementation Method 2
comparing a voltage at the first end of the connection with a reference voltage
Data Source
AI summary
A connection testing apparatus, a connection testing method, and a chip using the same are provided. The method can be used for testing connections between chips, so as to solve the problems that a conventional multi-chip connection test needs a plenty of test patterns, resulting in a long test time and a high test cost, and the condition of a connection failure is hard to be analyzed after a test failure. In the present invention, a voltage variation caused when an ESD element in a chip is conducted and a comparison circuits are used to determine whether a connection is correct. Furthermore, the test apparatus is built in the chip, so that the connection test may be accomplished quickly and efficiently. Once a connection failure occurs, the failed connection pin can also be found, so as to be favorable for engineering analysis and thereby effectively saving the test cost.