Chip-Correct ECC Coding With Reduced Check-Bit Overhead
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Solution Overview
Problem
Existing error correction code (ECC) schemes, such as SEC/DED and Reed-Solomon codes, face challenges in detecting and correcting multibit errors caused by both hard and soft errors in memory chips, often requiring excessive check bits, which can be cost-prohibitive, while returning to fewer check bits compromises reliability.
Innovation Solution
A chip-correct ECC scheme that implements fewer check bits than Reed-Solomon codes by using a combination of magnitude and locator check symbols, where each codeword includes b-bit portions and w check bits, with the locator check symbol generated to satisfy specific matrix multiplication equations, allowing for error detection and location with reduced overhead.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If Reed-Solomon codes are used to correct symbol errors in memory chips, then error detection and correction capability is improved, but the number of check bits required increases significantly
Solution Approach 1:
The invention segments the error correction problem into two distinct parts: magnitude detection (requiring b check bits) and location identification (requiring w check bits). This segmentation allows the system to use different coding strategies for each function, optimizing the total check bit requirement compared to traditional Reed-Solomon approaches that treat both functions uniformly.
Solution Approach 2:
The invention changes the parameter representation by using a mixed-radix approach where magnitude is represented in b bits and location in w bits (where w < b). This parameter change allows for more efficient encoding by matching the bit allocation to the actual information requirements of each error correction function, reducing overall overhead.
2Device complexity
If fewer check bits are used to reduce cost, then device complexity is reduced, but error locatability and correction reliability deteriorate
Solution Approach 1:
The invention introduces an intermediary approach by using a simplified location code (w bits) that works in conjunction with the magnitude code (b bits). This intermediary location mechanism provides sufficient error identification capability without requiring the full b-bit overhead of traditional Reed-Solomon location codes, thus reducing complexity while maintaining reliability.
Solution Approach 2:
The invention applies partial action by using only w bits for location instead of the full b bits that would be required for complete symbol identification. This partial approach is sufficient because the location only needs to identify which of the n symbols contains an error, not the full magnitude information, thereby reducing overhead while maintaining adequate error locatability.
Data Source
AI summary
An apparatus comprises an encode circuit coupled to receive input data and configured to generate corresponding codewords and a decode circuit coupled to receive codewords and detect an error in the codewords (and may, in some cases, correct the error). Each codeword comprises a plurality of b-bit portions (b is an integer greater than one). Additionally, each codeword comprises a first set of b check bits used to detect a magnitude of an error in a b-bit portion of the plurality of b-bit portions. Each codeword further comprises a second set of w check bits used to locate which one of the plurality of b-bit portions is the b-bit portion containing the error (w is an integer greater than zero and less than b).