Semiconductor Chip Crack Stop Structure With Compressive Edge Stress

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Solution Overview

Problem

Semiconductor chips are prone to mechanical damage during and after singulation, leading to significant reduction in fracture strength due to sub-micron cracks on chip sidewalls, which current crack stop structures fail to effectively prevent without compromising electrical functionality.

Innovation Solution

Implementing a crack stop structure with recesses filled with a metal material having intrinsic tensile stress that induces compressive stress in the chip periphery, counteracting crack formation and growth by pre-stressing the periphery into a compressive state.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If current crack stop structures are introduced between the chip sidewall and electrically active area, then crack propagation is reduced, but the distance between sidewall and electrically active area increases, reducing manufacturing efficiency

Engineering Contradiction:
Improvecrack propagation resistanceVSAvoidmanufacturing efficiency
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The patent changes the stress state parameter of the crack stop structure from neutral or tensile to compressive. By introducing compressive stress in the CSS, cracks must overcome this compressive force before propagating into the active area, significantly improving crack resistance without requiring large distances. The compressive stress is achieved through specific material selection and structural design of the CSS.

Inventive Principle:
Principle #35Parameter changes

Solution Approach 2:

The patent applies different stress characteristics to different regions: the CSS is designed to have compressive stress locally at the critical interface between sidewall and active area, while the rest of the chip maintains its normal stress state. This localized compressive stress application provides targeted crack protection without affecting the overall chip design or requiring large margins.

Inventive Principle:
Principle #3Local quality

2Area of stationary object

If crack stop structures are placed close to the electrically active area to minimize semiconductor area loss, then area utilization improves, but the structure must be optimized for electrical performance which may compromise crack stopping capability

Engineering Contradiction:
Improveusable semiconductor areaVSAvoidcrack stop effectiveness
Core Design Contradiction:
Area of stationary objectVSReliability

Solution Approach 1:

The patent changes the stress parameter of the CSS to compressive, which fundamentally improves crack stopping capability. This allows the CSS to be placed immediately adjacent to the electrically active area without compromising reliability, as the compressive stress provides strong crack resistance even in compact configurations.

Inventive Principle:
Principle #35Parameter changes

Solution Approach 2:

The patent designs the CSS to serve multiple functions simultaneously: it acts as an electrical isolation structure (blocking electrical paths between sidewall and active area) and as a mechanical crack stop (providing compressive stress to prevent crack propagation). This multi-functionality allows the CSS to be positioned close to the active area without sacrificing either electrical performance or crack resistance.

Inventive Principle:
Principle #6Universality (Multi-functionality)

3Reliability

If conventional crack stop structures use dielectric or low-stress metal materials for electrical performance, then electrical functionality is maintained, but fracture strength improvement is limited

Engineering Contradiction:
Improveelectrical functionalityVSAvoidfracture strength
Core Design Contradiction:
ReliabilityVSStrength

Solution Approach 1:

The patent changes the stress parameter of the CSS from neutral or tensile to compressive. This compressive stress state fundamentally improves fracture strength by preventing crack initiation and propagation. The patent achieves this through specific material selection (metals with high intrinsic compressive stress) and structural design, while maintaining electrical isolation functionality.

Inventive Principle:
Principle #35Parameter changes

Solution Approach 2:

The patent employs composite material strategies where the CSS combines materials with complementary properties: one material provides electrical isolation (dielectric properties) while another provides mechanical strength and compressive stress (metal properties). This composite approach allows the CSS to simultaneously achieve both electrical functionality and enhanced fracture strength.

Inventive Principle:
Principle #40Composite materials

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The pre-stressed crack stop structure enhances fracture strength, allows for a more compact design, increases usable wafer area, and reduces manufacturing costs by preventing crack propagation without adverse effects on electrical performance.

Implementation Method 1

the metal material has an intrinsic tensile stress at room temperature high enough to induce compressive stress in at least a region of the periphery of the semiconductor chip

Methodology Applied
Scientific EffectStress induction:

Data Source

PatentUS12406940B2Semiconductor chip having a crack stop structure
Publication Date: 2025.09.02 INFINEON TECHNOLOGIES AG
  • US12406940B2 patent drawing
  • US12406940B2 patent drawing
  • US12406940B2 patent drawing

AI summary

A semiconductor chip having a crack stop structure is disclosed. The crack stop structure includes one or more recesses formed in the semiconductor chip. The one or more recesses extend adjacent to and along a periphery of the semiconductor chip. The one or more recesses are filled with a metal material. The metal material has an intrinsic tensile stress at room temperature that induces compressive stress in at least a region of the periphery of the semiconductor chip.