Semiconductor Chip Crack Stopper for Wire Bonding Durability
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Solution Overview
Problem
Semiconductor chip interlayer insulation layers experience reduced durability and cracking due to external pressure during the wire bonding process, leading to potential signal delays and reliability issues.
Innovation Solution
Incorporating a crack stopper structure composed of conductive layers and vias surrounding the bonding pad, positioned at a lower level than the pad, to absorb and prevent crack propagation, while maintaining the integrity of the interlayer insulation layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If pressure is applied to the bonding pad during wire bonding process, then wire attachment is achieved, but cracks occur in the interlayer insulation layer
Solution Approach 1:
The patent applies preliminary action by forming the crack stopper structure (comprising conductive layers and vias) in advance within the interlayer insulation layer, before the wire bonding process occurs. This pre-positioned structure is strategically located around the bonding pad to intercept and stop cracks before they can propagate through the interlayer insulation layer during the subsequent pressure application in wire bonding, thus preventing damage while maintaining bonding reliability
Solution Approach 2:
The crack stopper structure serves as an intermediary element between the bonding pad and the interlayer insulation layer. It absorbs and redirects the stress concentration that occurs during wire bonding, acting as a mediator that prevents direct transmission of harmful forces to the interlayer insulation layer, thereby maintaining both bonding effectiveness and structural integrity
2Loss of time
If structures are added to reduce RC value, then signal delay is reduced, but interlayer insulation layer durability is reduced
Solution Approach 1:
The patent applies local quality by differentiating the structural characteristics of the interlayer insulation layer in different regions. Around the bonding pad area, the layer includes the crack stopper structure with conductive layers and vias to enhance durability. In other regions away from the bonding pad, the interlayer insulation layer maintains its original design optimized for low RC value, thus achieving both signal speed and durability where needed
Data Source
AI summary
Provided are a semiconductor chip, a semiconductor package and a fabricating method thereof, which can reduce or prevent cracks from being generated or propagated due to an external pressure. The semiconductor chip includes a semiconductor substrate including a first region and a second region, a plurality of interlayer insulation layers formed on the semiconductor substrate, a first crack stopper formed in the plurality of interlayer insulation layers of the first region, an interconnector formed in the plurality of interlayer insulation layers of the second region, a pad wire formed on the plurality of interlayer insulation layers, electrically connected to the interconnector in the second region and extending to the first region, a bonding pad on the plurality of interlayer insulation layers of the first region, electrically connected to the pad wire, and a protection layer covering the pad wire and exposing the bonding pad. The first crack stopper is positioned at a lower level than the bonding pad and is formed to completely surround the bonding pad while not overlapping with the bonding pad and not being connected to the pad wire.