Chip-Cross Interconnect System Dynamic Bandwidth Negotiation
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Solution Overview
Problem
Conventional interconnect systems, such as those using PCI Express (PCIe), often experience data congestion due to inconsistent bandwidth at transmission and receiving terminals, leading to suboptimal bandwidth utilization and inefficient data transmission.
Innovation Solution
A chip-cross interconnect system with a plurality of sockets interconnected through a first interconnect interface (ZPI) and dies interconnected through a second interconnect interface (ZDI), utilizing packet-based communication with headers and check codes to establish and maintain communication, and dynamically adjusting data payload size based on congestion levels to optimize bandwidth utilization and reduce delay.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional PCIe transmission is used, then data transmission can be implemented, but bandwidth utilization is low due to inconsistent bandwidth at transmission and receiving terminals causing data congestion
Solution Approach 1:
The patent implements dynamic bandwidth adjustment by allowing the receiving terminal to negotiate and request different bandwidth levels from the transmission terminal. The system transitions from fixed PCIe bandwidth to dynamic bandwidth allocation, enabling the receiving terminal to request higher bandwidth when needed and the transmission terminal to adjust accordingly, thereby resolving the bandwidth mismatch that causes congestion and improving overall bandwidth utilization.
Solution Approach 2:
The patent changes the bandwidth parameter from a fixed value to a negotiable variable. The receiving terminal can request different bandwidth levels (e.g., 4GT/s, 8GT/s, 16GT/s) based on its current needs, and the transmission terminal adjusts the actual transmission bandwidth accordingly. This parameter flexibility eliminates the bandwidth inconsistency problem and reduces transmission delays.
2Speed
If bandwidth is increased to reduce congestion, then data transmission speed improves, but circuit complexity increases
Solution Approach 1:
The patent segments the bandwidth negotiation process into distinct functional modules: a bandwidth request generation module at the receiving terminal, a bandwidth negotiation module at the transmission terminal, and a bandwidth adjustment module. This segmentation allows the complex bandwidth management functionality to be implemented through modular components rather than requiring complete circuit redesign, thus achieving high transmission speeds with manageable circuit complexity.
Solution Approach 2:
The patent implements a universal bandwidth negotiation mechanism that can operate across different PCIe generation levels (Gen3, Gen4, Gen5) and different bandwidth configurations (4GT/s, 8GT/s, 16GT/s). The same negotiation protocol and control logic can handle various bandwidth scenarios, eliminating the need for separate dedicated circuits for each bandwidth level and reducing overall circuit complexity while maintaining high transmission speeds.
Data Source
AI summary
A interconnect system, including a plurality of sockets and a first interconnect interface. Any two of the sockets are accessible to each other's hardware resources by transmitting a first packet and a second packet through the first interconnect interface. The first packet includes first interconnect information, used for establishing communication between the two sockets. The second packet includes a first data payload, loaded from one of the two sockets. The sockets include a first socket and a second socket, configured to be interconnected with each other through the first interconnect interface.