3D Chip Cross-Section Rendering for Defect Identification
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Solution Overview
Problem
Current semiconductor failure analysis is hindered by the difficulty in accurately identifying the location of defects within integrated circuits before destructive cutting, leading to potential destruction of the defect site and inefficient diagnosis.
Innovation Solution
A computer-implemented method for identifying and rendering a three-dimensional view of the integrated circuit's design portion corresponding to a physical portion with potential defects, using layout-driven navigation to precisely locate and visualize the defect area before physical cutting, thereby minimizing errors and improving analysis efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If physical cutting is performed to examine chip cross-section, then defect identification is enabled, but the defect site may be destroyed and analysis time is increased
Solution Approach 1:
The system performs preliminary actions by rendering a three-dimensional view of the chip cross-section before physical cutting. This allows the analyst to pre-identify the precise location and characteristics of the defect site, plan the optimal cutting path, and avoid unnecessary physical intervention, thereby reducing analysis time while maintaining identification accuracy.
Solution Approach 2:
The system creates a virtual copy of the chip cross-section through three-dimensional rendering based on design information. This digital replica allows examination of the defect site without physical damage to the actual chip, enabling multiple analysis attempts and detailed inspection without time loss from repeated physical cutting.
2Loss of time
If surface examination is performed without cutting, then analysis time is reduced, but the structure and materials beneath the surface remain unknown
Solution Approach 1:
The system performs preliminary rendering of the three-dimensional chip cross-section before physical cutting. This allows the analyst to pre-identify the precise location and characteristics of the defect site, plan the optimal cutting path, and avoid unnecessary physical intervention, thereby reducing analysis time while maintaining identification accuracy.
Solution Approach 2:
The system creates a virtual copy of the chip cross-section through three-dimensional rendering based on design information. This digital replica allows examination of the defect site without physical damage to the actual chip, enabling multiple analysis attempts and detailed inspection without time loss from repeated physical cutting.
3Measurement precision
If layout-driven navigation is used to locate defect area, then location accuracy is improved, but device complexity increases
Solution Approach 1:
The layout-driven navigation system serves multiple functions: it provides precise location identification, generates three-dimensional renderings, guides physical cutting operations, and enables virtual examination. By consolidating these functions into a single integrated system, the patent reduces overall device complexity while maintaining high location accuracy.
Solution Approach 2:
The three-dimensional rendering acts as an intermediary between the layout information and the physical chip. It translates design data into a visual representation that guides both virtual analysis and physical cutting, simplifying the navigation process and improving location accuracy without requiring complex direct manipulation systems.
Data Source
AI summary
A defective integrated circuit (IC) is analyzed to identify a portion of the integrated circuit possibly containing an electrical defect. A computer is used to process the design information of the integrated circuit and to navigate to the physical portion of the integrated circuit where the potential electrical defect might be found. The design information includes information on the layout and the technology used to fabricate the integrated circuit. A three-dimensional view of the portion of the design of the integrated circuit where the electrical defect might be found is rendered, based on the design information for the integrated circuit.