Chip Data Path Gating for Low Power Testing
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Solution Overview
Problem
Current chip testing methods consume high power during the test mode, increasing costs and reducing reliability, while also affecting the speed performance in functional mode, as the circuit activity is higher in test modes compared to functional modes.
Innovation Solution
Incorporating a data path gating system that detects a test enable signal to disable data path functions when the test mode is irrelevant to the data path function of the combinational logic, thereby reducing power consumption without compromising speed performance in functional mode.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If chip testing is implemented using conventional DFT methods with additional logics, then testing reliability is improved, but power consumption during test mode increases significantly
Solution Approach 1:
The patent applies dynamics by making the data path gating controllable and switchable between different states. The data path gating can be dynamically enabled or disabled based on the test mode, allowing the circuit to adapt its power consumption characteristics. Specifically, the gating is disabled during test modes (scan test, boundary scan, JTAG) to reduce power consumption, while being enabled during functional modes to maintain normal operation, thus resolving the contradiction between testing reliability and power consumption.
Solution Approach 2:
The patent changes the operational state parameter of the data path gating from a fixed state to a variable state that can be controlled. By introducing a control signal that can set the gating to enabled or disabled states, the system can adjust its power consumption parameter according to the operational mode. This parameter change allows the circuit to consume less power during test modes while maintaining full functionality during normal operation.
2Reliability
If circuit activity is increased during test mode to improve testing effectiveness, then testing quality is improved, but speed performance in functional mode is affected
Solution Approach 1:
The data path gating is designed as a dynamic component that can switch between enabled and disabled states based on operational mode. During test modes, the gating is disabled to allow high circuit activity and signal propagation for thorough testing. During functional modes, the gating is enabled to maintain the original circuit behavior and speed performance. This dynamic switching resolves the contradiction by allowing high activity only when needed for testing.
Solution Approach 2:
The patent segments the data path into controllable sections using the data path gating. By dividing the data path into gated and ungated sections, the system can selectively control signal flow during different operational modes. During test modes, the gating is disabled to allow signals to propagate through the entire data path for comprehensive testing. During functional modes, the gating is enabled to maintain normal signal flow and speed performance, thus resolving the contradiction between testing quality and speed performance.
Data Source
AI summary
A chip, a chip testing method and an electronic device are provided. The chip includes a combinational logic and a data path gating; the data path gating includes a first input terminal and an output terminal, the first input terminal of the data path gating detects a test enable signal, and the output terminal of the data path gating is connected to the combinational logic; the test enable signal is used to switch a test mode of the chip; the data path gating is configured to output a data path gating control signal to the combinational logic, in a case where the detected test enable signal indicates that a current test mode is irrelevant to a data path function of the combinational logic; and the combinational logic is configured to disable the data path function after receiving the data path gating control signal, to disable data path toggling.