Multi-Channel Chip Data Transfer Without Packet Assembly
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Solution Overview
Problem
Current data transmission between multiple chips in computing systems is limited, leading to delays and increased power consumption due to data segmentation and packet assembly in multi-channel transmission.
Innovation Solution
Implement concurrent data transmission through multiple transmission channels by directly reading and writing data across chips using segment addresses associated with specific channels, eliminating the need for data segmentation and packet assembly.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If data segmentation and packet assembly are performed for multi-channel transmission, then data transmission capacity is improved, but data transmission delay increases
Solution Approach 1:
The patent divides the address space into multiple segment addresses, each corresponding to a different transmission channel. This allows data to be segmented across multiple channels simultaneously without requiring complex packet assembly at the destination, as each segment address directly maps to its destination channel.
Solution Approach 2:
The system performs preliminary address mapping by associating segment addresses with transmission channels before data transmission begins. This pre-establishes the routing path for each data segment, eliminating the need for complex packet assembly operations at the destination and reducing transmission delay.
2Quantity of substance
If data segmentation and packet assembly are performed for multi-channel transmission, then data transmission capacity is improved, but power consumption increases
Solution Approach 1:
The patent segments the address space rather than the data itself, allowing direct mapping of address segments to transmission channels. This eliminates the need for complex packet assembly operations that consume significant power, while still enabling parallel data transmission across multiple channels.
Solution Approach 2:
The patent replaces the mechanical packet assembly process with a direct address mapping mechanism. Instead of physically assembling packets at the destination, the system uses address-based routing to direct data segments to their correct destinations, significantly reducing the computational power required for data transmission.
3Quantity of substance
If multiple transmission channels are used for data transmission, then data transmission capacity is improved, but system complexity increases
Solution Approach 1:
The patent segments the address space into multiple segment addresses that can be directly associated with different transmission channels. This simple addressing scheme allows multiple channels to operate in parallel without requiring complex packet assembly or routing logic, thereby reducing system complexity while maintaining high data transmission capacity.
4Reliability
If packet assembly is performed based on sequence of data, then data integrity is ensured, but data transmission delay increases due to waiting for late arrival packets
Solution Approach 1:
The system performs preliminary association between segment addresses and transmission channels before data transmission. This pre-establishes the correct routing path for each segment, allowing destination systems to directly retrieve data segments without waiting for packet assembly, thereby ensuring data integrity while eliminating delays caused by late-arriving packets.
Data Source
AI summary
A system includes a first subsystem and a second subsystem. When there is to-be-transmitted data between the first subsystem and the second subsystem, a processor of the first subsystem is configured to obtain a first address in the storage device of the first subsystem and a second address in a storage device of the second subsystem. The processor of the first subsystem is configured to associate segment addresses in the second address with transmission channels. When the second address is a source address, the processor of the first subsystem is configured to: read data at the segment address through a transmission channel associated with the segment address, and store the read data at an address that is in the first address and that corresponds to the segment address.


