Chip-to-Chip Data Transfer with Parallel Hardware Cryptography
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Solution Overview
Problem
Modern control units face risks of data interception and tampering during chip-to-chip communication, which is unencrypted and autonomously managed, straining CPU resources and compromising security.
Innovation Solution
A data processing device with integrated cryptography units and communication interfaces in each computing unit for parallel encryption, decryption, and transmission, using block-by-block and packet-by-packet methods to ensure secure and efficient data transfer without CPU overload.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If data transmission is carried out unencrypted via C2C interface to ensure high bandwidth and low latency, then communication speed is improved, but security deteriorates due to risk of data interception and tampering
Solution Approach 1:
The data transmission process is segmented into separate functional components: encryption unit, authentication unit, and data transmission unit. The encryption unit processes data independently before transmission, while the authentication unit verifies data integrity separately, allowing security operations to occur in parallel with transmission operations, thus maintaining high speed while ensuring security
Solution Approach 2:
An encryption unit and authentication unit are introduced as intermediary components between the CPU and the C2C interface. These intermediaries handle security-critical operations (encryption and authentication) independently, allowing the main data transmission to proceed at high speed through the C2C interface without security being a bottleneck, while still providing the required security protection
2Reliability
If CPU is used for encryption and decryption operations to ensure security, then data security is improved, but CPU performance deteriorates due to resource consumption
Solution Approach 1:
The encryption and decryption functions are extracted from the CPU and implemented as separate, dedicated hardware units (encryption unit and authentication unit). This extraction allows the CPU to focus on its primary processing tasks while security operations are handled independently by specialized components, thus maintaining data security without consuming CPU resources
Solution Approach 2:
The system implements self-service security operations where the encryption unit and authentication unit automatically perform encryption and authentication tasks without requiring CPU intervention. These units operate autonomously, receiving data from memory or other sources and processing it through security operations, thereby protecting CPU performance while ensuring data security
3Reliability
If encryption is performed on the entire message to ensure security, then data security is improved, but processing time deteriorates due to waiting for complete message
Solution Approach 1:
The encryption unit performs preliminary encryption operations on data blocks as they become available, rather than waiting for the complete message. This allows encryption to start in advance and proceed continuously, reducing the overall processing time while maintaining security. Similarly, the authentication unit performs preliminary authentication checks on received data blocks before complete message assembly
Solution Approach 2:
The message is segmented into smaller data blocks that can be encrypted and authenticated independently and in parallel. The encryption unit processes multiple data blocks simultaneously through parallel operations, and the authentication unit verifies authentication tags for each block separately, eliminating the need to wait for the entire message before security operations can proceed
Data Source
AI summary
A data processing device for a control unit. The data processing device includes first and second computing units. The first computing unit includes a first memory device configured to provide first data to be sent, a first cryptography unit configured to encrypt the first data to be sent, and a first serial communication interface configured to send the first encrypted data to be sent from the first computing unit to the second computing unit. The second computing unit includes a second serial communication interface configured to receive the first, encrypted data from the first computing unit, a second cryptography unit configured to decrypt the first, received, encrypted data, and a second memory device configured to store the first, received, decrypted data.