Chip Data Transmission Interface Adaptability
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Solution Overview
Problem
Current chip interface technologies face challenges in flexibility, compatibility, and reliability due to increasing bandwidth requirements and complex design needs, particularly with high-speed SerDes interfaces, leading to instability and increased design and manufacturing costs.
Innovation Solution
A chip-based data transmission method that performs protocol layer processing, including encapsulation, CRC calculation, striping, and line order adjustment, and meta-frame layer processing, such as encoding, framing, and tag insertion, to dynamically adjust data transmission across multiple physical channels, ensuring bandwidth utilization and reducing design risks and costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If multiple interfaces with different line speed bandwidths are integrated on one chip to meet different application requirements, then the adaptability and versatility of the chip interface is improved, but the device complexity and design cost increase
Solution Approach 1:
The patent implements a universal interface design where a single chip interface can operate at multiple line speeds (e.g., 10.3125G, 25.78125G, 51.5625G, 103.125G) by dynamically adjusting the working modes of SerDes units and physical channels. This eliminates the need for separate dedicated interfaces for each bandwidth requirement, thereby improving adaptability while controlling complexity through standardized architecture
Solution Approach 2:
The interface employs dynamic configuration capabilities where the number of working SerDes units and physical channels can be flexibly adjusted based on actual bandwidth requirements. The system can dynamically select and activate appropriate numbers of physical channels (e.g., 2, 4, 8, 12, 16, 20, or 24 channels) to match different application scenarios, achieving versatility without requiring all possible configurations to be permanently built
2Productivity
If the SerDes interface rate is increased to meet higher bandwidth requirements, then the productivity and data transmission capability are improved, but the reliability and stability of the interface deteriorate
Solution Approach 1:
The high-speed data transmission interface is segmented into multiple independent physical channels, each operating at lower individual rates but collectively providing high aggregate bandwidth. For example, instead of using a single 200G interface, the system divides data into multiple 10.3125G or 25.78125G channels that are processed independently and then reassembled at the receiving end. This segmentation reduces the stability challenges associated with ultra-high-speed single-channel transmission while maintaining overall high productivity
Solution Approach 2:
Different physical channels can be configured with different working parameters and transmission characteristics based on their specific quality and stability. The system can selectively activate channels with better signal quality and adjust local transmission parameters (such as encoding schemes, equalization settings) to optimize reliability for each channel while maintaining high overall bandwidth
3Productivity
If more physical channels are added to increase data bandwidth, then the productivity is improved, but the device complexity and design difficulty increase
Solution Approach 1:
Multiple physical channels are merged into a unified management framework with common control logic, configuration mechanisms, and processing pipelines. The system uses a single set of control registers, configuration interfaces, and protocol handling logic to manage all physical channels, eliminating the need for separate management systems for each channel. This merging approach allows the system to scale from 2 to 24 physical channels without proportionally increasing design complexity
Solution Approach 2:
The chip is designed with the capability to support a maximum number of physical channels (e.g., 24 channels), but in practice, only the necessary number of channels are activated based on specific application requirements. This allows the system to provide full scalability potential while actually using only the required resources, thereby avoiding the complexity overhead of fully implementing and managing all possible channels in every deployment scenario
Data Source
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AI summary
Disclosed is a chip-based data transmission method for a data sending side. The method includes that protocol layer processing is performed on input data, and the data after the protocol layer processing is mapped to each physical channel for transmission; meta-frame layer processing is performed on the data transmitted by each physical channel, and the data after the meta-frame layer processing is sent. Another chip-based data transmission method for a data receiving side is provided which includes that meta-frame layer processing is performed on data received by each physical channel, the data after the meta-frame layer processing is mapped to a protocol layer for transmission, and the protocol layer processing is performed on the data transmitted by the protocol layer, and the data after the protocol layer processing is sent. A chip-based data transmission device and system, and a computer storage medium are also provided.