On-Chip Delay Capture Circuit for Fine Signal Timing Measurement
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Solution Overview
Problem
Conventional signal measurement techniques for electronic circuits are complex, costly, and offer limited measurement granularity or resolution, particularly in System-on-a-Chip (SoC) applications, requiring expensive and cumbersome external automated test equipment.
Innovation Solution
A high precision on-die delay measurement circuit using two delay chains with different tap delays, connected to capture flip-flops, allows for precise measurement of signal transitions by deriving measurement resolution from the difference in delay between the chains, and can be calibrated using a ring oscillator configuration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If conventional external automated test equipment is used for signal measurement, then measurement capability is provided, but cost and device complexity increase significantly
Solution Approach 1:
The patent extracts the measurement function from external test equipment and implements it directly on the chip using integrated delay chains and capture flip-flops. This eliminates the need for expensive external ATE tools while maintaining measurement capability through on-chip delay measurement circuits.
Solution Approach 2:
The measurement circuit serves itself by using on-chip resources (delay chains, flip-flops, logic circuits) to perform measurements without requiring external test equipment. The circuit self-calibrates and self-measures using internal clock signals and delay elements, making the system self-sufficient for timing measurements.
2Device complexity
If delay-chain circuits with single capture flip-flop are used, then on-die measurement is achieved, but measurement resolution is limited
Solution Approach 1:
The patent divides the measurement function into multiple segments by using multiple capture flip-flops (first, second, third, and fourth capture flip-flops) that capture signals at different delay points. This segmentation allows measurement of multiple delay intervals, improving resolution beyond what a single capture flip-flop can achieve.
Solution Approach 2:
The patent adds temporal dimension to the measurement by using multiple clock cycles and multiple capture points. Instead of measuring only within a single clock cycle, the circuit captures signals across multiple cycles using different capture flip-flops, effectively adding a time dimension that improves measurement granularity and resolution.
3Measurement precision
If multiple capture flip-flops with identical clock signal are used, then signal skew measurement is enabled, but circuit complexity increases
Solution Approach 1:
The patent merges the measurement of multiple parameters (propagation delay and signal skew) into a single integrated circuit structure. The same set of delay chains and capture flip-flops used for propagation delay measurement are also utilized for signal skew measurement, eliminating the need for separate measurement circuits and reducing overall complexity.
Solution Approach 2:
The measurement circuit is designed to be multi-functional, serving both propagation delay measurement and signal skew measurement purposes. The delay chains and capture flip-flops can be configured to measure different timing parameters using the same hardware resources, making the circuit universal and reducing the need for additional dedicated circuits.
4Measurement precision
If DLL circuits with interpolator are used, then phase measurement is achieved, but device complexity and cost increase
Solution Approach 1:
The patent replaces complex, expensive DLL circuits with simpler, cheaper delay chain structures. Instead of using sophisticated delay locked loops with interpolators, the invention uses basic delay elements and capture flip-flops that are less complex and more cost-effective while achieving comparable or sufficient measurement precision for the application.
Data Source
AI summary
A method and circuit for providing on-chip measurement of the delay between two signals includes first and second delay chains (241, 242) having different delay values connected to sampling latches (222-227) which each include a data input coupled between adjacent delay elements of the first delay chain and a clock input coupled between adjacent delay elements of the second delay chain, thereby capturing a high precision delay measurement for the signals.