Chip Delay-Path Configuration for Robust Physically Obfuscated IDs
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Solution Overview
Problem
The reverse engineering of integrated circuits poses a significant threat to the semiconductor industry, as it enables the cloning of ICs, necessitating techniques that make cloning difficult and unprofitable, while ensuring robust generation of physically obfuscated information to prevent misidentification and complex error correction.
Innovation Solution
A method involving delay stages with pairs of delay elements, where the least delayed element is determined for each stage, and configuration information is used to connect these elements in series to form paths, generating physically obfuscated information that is robust to process, voltage, and temperature fluctuations, using multiplexers and bypass elements to enhance security.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If physically obfuscated information is generated using delay elements, then security against cloning is improved, but sensitivity to process, voltage, and temperature fluctuations increases
Solution Approach 1:
The patent changes the parameter being measured from absolute delay time to relative delay difference. By comparing which of two delay elements is faster rather than measuring absolute delay values, the system becomes insensitive to process, voltage, and temperature fluctuations that affect all delay elements uniformly, while still capturing the unique fingerprint caused by manufacturing variations.
Solution Approach 2:
Instead of trying to make delay elements identical through precise manufacturing, the patent inverts the approach by deliberately exploiting the variations. It configures circuits to amplify and measure the differences between delay elements, turning the manufacturing imprecision into the security feature itself - the unique fingerprint that prevents cloning.
2Reliability
If complex error correction is implemented to handle POC value variations, then reliability of POC value recognition is improved, but device complexity increases
Solution Approach 1:
The patent incorporates error correction capability into the POC value generation process itself by using redundant delay elements and majority voting logic. This beforehand cushioning ensures that even if some delay elements are affected by fluctuations, the correct POC value is still generated through the voting mechanism, maintaining reliability without requiring separate complex error correction systems.
3Reliability
If more delay stages and delay elements are used to enhance obfuscation, then security against reverse engineering is improved, but manufacturing precision requirements increase
Solution Approach 1:
The patent segments the delay path into multiple stages, each with pairs of delay elements. This segmentation allows the system to build up the fingerprint through cumulative delay differences across stages rather than relying on a single complex delay element, enhancing security while managing manufacturing precision requirements through modular design.
Solution Approach 2:
The patent creates asymmetric delay paths by configuring odd-numbered and even-numbered delay stages differently - odd stages connect faster elements sequentially while even stages connect slower elements sequentially. This asymmetric configuration maximizes the delay difference between the two main paths, enhancing the obfuscation effect without requiring ultra-precise matching of all delay elements.
Data Source
AI summary
A method for providing configuration information for generating physically obfuscated information on a chip with a plurality of circuits, which have a plurality of delay stages, is provided, wherein each delay stage has at least two delay elements, and the method includes determining, for each of the circuits, for each delay stage, which of the delay elements of the delay stage has the least delay among the delay elements of the delay stage, determining configuration information depending on the determined delay elements, which configuration information specifies a configuration of the circuit for each of the circuits, in which the delay elements of different delay stages are connected in series in such a way that at least one path from an input of the circuit to an output of the circuit is formed and storing the determined configuration information.