On-Chip Delay Monitoring Circuitry for Voltage-Shifted Timing
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Solution Overview
Problem
Integrated circuits face timing violations due to transient supply voltage and temperature variations, which are not effectively managed by existing supply voltage regulators, leading to uncertainty in delay measurements and potential malfunctions.
Innovation Solution
An on-chip self-calibrating delay monitoring circuitry is implemented, comprising a programmable delay line, time-to-digital converter, and feedback loop, which estimates and adjusts delays in real-time to match target values, thereby minimizing timing violations caused by supply voltage and temperature changes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the size of MOS transistors is decreased to increase integration density, then the supply voltage can be reduced, but the delay becomes more sensitive to transient variations in supply voltage and temperature
Solution Approach 1:
The patent implements a feedback mechanism where delay monitoring circuitry continuously measures the actual delay of critical paths and compares it against target delay values. When timing violations are detected or predicted, the system adjusts supply voltage or clock frequency to maintain reliable operation. This closed-loop feedback resolves the contradiction by dynamically compensating for the increased sensitivity to voltage and temperature variations that results from transistor scaling.
Solution Approach 2:
The patent employs preliminary action by proactively detecting delay variations before they cause timing violations. The delay monitoring circuitry continuously tracks delay parameters and predicts potential timing failures, allowing the system to adjust supply voltage or clock frequency in advance. This preventive approach addresses the increased delay sensitivity caused by transistor size reduction before it impacts circuit reliability.
2Loss of energy
If the supply voltage regulator is used to adapt supply voltage to changing requirements, then power dissipation can be optimized, but the transient response is slower than the time scale of on-chip IR drop events
Solution Approach 1:
The patent introduces delay monitoring circuitry as an intermediary between the supply voltage regulator and the critical circuits. This intermediary continuously measures delay parameters and provides real-time information about actual circuit performance. The monitoring circuitry enables the system to detect and respond to delay variations caused by IR drops, compensating for the slow response of the voltage regulator through active measurement and prediction capabilities.
Solution Approach 2:
The patent replaces reliance on the mechanical/electrical response of the supply voltage regulator with an electronic measurement and control system. Instead of depending solely on the regulator's transient response to correct voltage variations, the system uses electronic delay monitoring to detect and predict timing violations, then adjusts supply voltage or clock frequency through control logic. This substitution of measurement-based control for regulator-based correction resolves the speed mismatch.
3Reliability
If delay measurement is performed to ensure timing compliance, then timing violations can be detected, but uncertainty in measuring delay is introduced due to supply voltage variations
Solution Approach 1:
The patent implements self-service by using the delay monitoring circuitry to measure its own delay characteristics under actual operating conditions. The monitoring circuitry is designed to account for supply voltage variations and temperature effects by performing measurements in-situ rather than relying on external test equipment or theoretical models. This self-measurement approach ensures that the delay data reflects actual circuit behavior, improving both detection reliability and measurement precision.
Solution Approach 2:
The patent addresses measurement uncertainty by dynamically adjusting measurement parameters based on operating conditions. The system monitors supply voltage and temperature parameters and adapts its delay measurement and evaluation criteria accordingly. By changing measurement parameters to match actual operating conditions, the system maintains high precision in delay measurement even as voltage and temperature vary, resolving the contradiction between detection reliability and measurement precision.
4Productivity
If the clock frequency is increased to improve performance, then productivity increases, but the timing margin decreases making the circuit more susceptible to timing violations
Solution Approach 1:
The patent applies dynamics by making the clock frequency adjustable rather than fixed. The delay monitoring circuitry continuously evaluates actual delay parameters and provides feedback to dynamically adjust the clock frequency. When timing margins become insufficient due to process variations, temperature, or voltage changes, the system automatically reduces clock frequency to maintain reliable operation. Conversely, when conditions permit, the clock frequency can be increased to maximize productivity. This dynamic adjustment resolves the contradiction between achieving high productivity through increased clock frequency and maintaining sufficient timing margin for reliable operation.
Data Source
AI summary
The present disclosure relates to on-chip self calibrating delay monitoring circuitry.